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oxford semiconductor ltd. ? oxford semiconductor 2001 25 milton park, abingdon, oxon, ox14 4sh, uk ox16c950 rev b datasheet r1.2 ? may 2001 tel: +44 (0)1235 824900 fax: +44 (0)1235 821141 part no. OX16C950-PCC60-B f eatures ? single full-duplex asynchronous channel ? 128-byte deep transmitter / receiver fifo ? fully software compatible with industry standard 16c550 type uarts ? pin compatible with tl16c550b/c, st16c650 and tl16c750 ? ibm pc/at compatible ? baud rates up to 15 mbps in normal mode and 60mbps in external 1x clock mode ? readable fifo levels ? flexible clock prescaler from 1 to 31.875 ? isochronous mode using exter nal 1x baud rate clock up to 60mbps ? 9-bit data framing as well as 5,6,7 and 8 ? detection of bad data in the receiver fifo ? automated in-band flow control using programmable xon/xoff characters ? transmitter and receiver can be disabled ? automated out-of-band flow control using cts# / rts# and dsr# / dtr# ? readable in-band and out-of-band flow control status ? programmable special character detection ? arbitrary trigger levels for receiver and transmitter fifo interrupts and automatic in-band and out-of-band flow control ? transmitter idle interrupt (shift register and fifo both empty) ? optional infra-red (irda) receiver and transmitter operation ? rs-485 buffer enable signals ? software channel reset ? four byte device id ? sleep mode (low operating current) ? system clock up to 60 mhz (at 5v), 50 mhz at 3.3v ? 44 plcc and 48 tqfp packages ? 5 volts operation (plcc), 3.3/ 5v operation tqfp r ev b e nhancements the ox16c950b is an enhanced, fully backward-compatible revisi on of the ox16c950 rev a. the chief enhancements are as follows ? ? all known errata fixed ? enhanced features first offered in ox16pci954 added ? these include controls for sleep-mode sensitivity, ability to read fcr and good data status ? 3v operation possible with 48 pin tqfp ? enhanced isochronous clocking opti ons (optional inversions) ? enhanced system clock selection options (use of clksel as a clock input) ? readable txrdy, rxrdy status and forcing txrdy or rxrdy inactive hereafter ox16c950 rev b is simply referred to as ox16c950. ox16c950 rev b high performance uart with 128 byte fifos
oxford semiconductor ltd. ? oxford semiconductor 2001 25 milton park, abingdon, oxon, ox14 4sh, uk ox16c950 rev b datasheet r1.2 ? may 2001 tel: +44 (0)1235 824900 fax: +44 (0)1235 821141 part no. OX16C950-PCC60-B d escription the ox16c950 is a single-channel ultra-high performance uart offering data rates up to 15mbps and 128-deep transmitter and receiver fifos. deep fifos reduce cpu overhead and allow utilisation of higher data rates. it is software compatible with the widely used industry- standard 16c550 type devices and compatibles, as well as other ox16c95x family devices. it is pin-compatible with the tl16c550, st16c650 devices. in addition to increased performance and fifo size, the ox16c950 also provides enhanced features including improved flow control. automated software flow control using xon/xoff and automated hardware flow control using cts#/rts# and dsr#/dtr# prevent fifo over-run. flow control and interrupt thresholds are fully programmable and readable, enabling programmers to fine-tune the performance of their system. fifo levels are readable to facilitate fast driver applications. the addition of software reset enables recovery from unforeseen error condition allowing drivers to restart gracefully. the ox16c950 supports 9-bit data frames used in multi-drop industrial protocols. it also offers multiple external clock options for isochronous applications, e.g. isdn, xdsl. the ox16c950 is ideally suited to pc applications, such as high-speed com port add-in cards which enable pc users to take advantage of the maximum performance of analogue modems or isdn terminal adapters. it is also suitable for any equipment requiring high speed rs232/rs422/rs485 interfaces. fabricated in 0.6 m process, ox16c950 also has a low operating current and sleep mode for battery powered applications.
data sheet revision 1.2 page 3 ox16c950 rev b oxford semiconductor ltd. c ontents features....................................................................................................................... ................................................................ 1 rev b enhancements............................................................................................................. ................................................... 1 description .................................................................................................................... ............................................................. 2 contents ....................................................................................................................... ............................................................... 3 1 performance comparison ......................................................................................................... ..................................... 5 2 block diagram .................................................................................................................. ................................................... 6 3 pin information................................................................................................................ .................................................... 7 4 pin descriptions ............................................................................................................... ................................................... 8 4.1 f urther p in i nformation ............................................................................................................................... .................. 11 5 mode selection................................................................................................................. ................................................. 13 5.1 450 m ode ............................................................................................................................... ............................................ 13 5.2 550 m ode ............................................................................................................................... ............................................ 13 5.3 e xtended 550 m ode ............................................................................................................................... ........................... 13 5.4 750 m ode ............................................................................................................................... ............................................ 13 5.5 650 m ode ............................................................................................................................... ............................................ 13 5.6 950 m ode ............................................................................................................................... ............................................ 14 6 register description tables.................................................................................................... ................................... 15 7 reset configuration............................................................................................................ ........................................... 19 7.1 h ardware r eset ............................................................................................................................... ................................ 19 7.2 s oftware r eset ............................................................................................................................... ................................ 19 8 transmitter & receiver fifos................................................................................................... ................................... 20 8.1 fifo c ontrol r egister ?fcr? .......................................................................................................................... ............... 20 9 line control & status .......................................................................................................... .......................................... 21 9.1 f alse s tart b it d etection ............................................................................................................................... ................ 21 9.2 l ine c ontrol r egister ?lcr? .......................................................................................................................... ................. 21 9.3 l ine s tatus r egister ?lsr?.......................................................................................................................... .................... 22 10 interrupts & sleep mode........................................................................................................ ....................................... 23 10.1 i nterrupt e nable r egister ?ier? .......................................................................................................................... ........... 23 10.2 i nterrupt s tatus r egister ?isr? .......................................................................................................................... ........... 24 10.3 i nterrupt d escription ............................................................................................................................... ...................... 24 10.4 s leep m ode ............................................................................................................................... ........................................ 25 11 modem interface................................................................................................................ ............................................... 25 11.1 m odem c ontrol r egister ?mcr? .......................................................................................................................... ........... 25 11.2 m odem s tatus r egister ?msr? .......................................................................................................................... .............. 26 12 other standard registers ....................................................................................................... ................................... 27 12.1 d ivisor l atch r egisters ?dll & dlm?.................................................................................................................... ......... 27 12.2 s cratch p ad r egister ?spr? .......................................................................................................................... ................. 27 13 automatic flow control ......................................................................................................... ..................................... 28 13.1 e nhanced f eatures r egister ?efr?.......................................................................................................................... ...... 28 13.2 s pecial c haracter d etection ............................................................................................................................... .......... 29 13.3 a utomatic i n - band f low c ontrol ............................................................................................................................... .... 29 13.4 a utomatic o ut - of - band f low c ontrol ........................................................................................................................... 29 14 baud rate generation........................................................................................................... ......................................... 30 14.1 g eneral o peration ............................................................................................................................... ........................... 30 14.2 c lock p rescaler r egister ?cpr?.......................................................................................................................... .......... 31 14.3 t imes c lock r egister ?tcr?.......................................................................................................................... ................... 31 14.4 i nput c lock o ptions ............................................................................................................................... ......................... 33 14.5 ttl c lock m odule ............................................................................................................................... ............................ 33
data sheet revision 1.2 page 4 ox16c950 rev b oxford semiconductor ltd. 14.6 e xternal 1 x c lock m ode ............................................................................................................................... .................. 33 14.7 c rystal o scillator c ircuit ............................................................................................................................... ............. 33 15 additional features ............................................................................................................ ........................................... 34 15.1 a dditional s tatus r egister ?asr?.......................................................................................................................... ......... 34 15.2 fifo f ill levels ?tfl & rfl?.................................................................................................................... ........................ 34 15.3 a dditional c ontrol r egister ?acr?.......................................................................................................................... ...... 34 15.4 t ransmitter t rigger l evel ?ttl?.......................................................................................................................... ........... 36 15.5 r eceiver i nterrupt . t rigger l evel ?rtl? ....................................................................................................................... 36 15.6 f low c ontrol l evels ?fcl & fch?.................................................................................................................... .............. 36 15.7 d evice i dentification r egisters ............................................................................................................................... ....... 36 15.8 c lock s elect r egister ?cks? .......................................................................................................................... ................ 37 15.9 n ine - bit m ode r egister ?nmr? .......................................................................................................................... ............... 37 15.10 m odem d isable m ask ?mdm?.......................................................................................................................... ............... 38 15.11 r eadable fcr ?rfc? ...................................................................................................................... .............................. 38 15.12 g ood - data status register ?gds? .......................................................................................................................... .... 39 15.13 dma s tatus r egister ?dms? .......................................................................................................................... ............. 39 15.14 p ort i ndex r egister ?pix?.......................................................................................................................... .................. 39 15.15 c lock a lteration r egister ?cka?.......................................................................................................................... ..... 39 16 operating conditions ........................................................................................................... .......................................... 40 17 dc electrical characteristics.................................................................................................. ................................ 40 17.1 5v o peration ............................................................................................................................... ..................................... 40 17.2 3v o peration ............................................................................................................................... ..................................... 41 18 ac electrical characteristics.................................................................................................. ................................ 42 18.1 5v o peration ............................................................................................................................... ..................................... 42 18.2 3v o peration ............................................................................................................................... ..................................... 43 19 timing waveforms............................................................................................................... .............................................. 44 20 package information............................................................................................................ .......................................... 46 21 ordering information ........................................................................................................... ......................................... 47 notes.......................................................................................................................... .................................................................. 48 contact details ................................................................................................................ ...................................................... 49
data sheet revision 1.2 page 5 ox16c950 rev b oxford semiconductor ltd. 1 p erformance c omparison feature ox16c950 16c450 16c550 16c650 16c750 external 1x baud rate clock yes no no no no max baud rate in normal mode 15 mbps 115 kbps 115 kbps 1.5 mbps 1 mbps max baud rate in 1x clock mode 60 mbps n/a n/a n/a n/a fifo depth 128 1 16 32 64 sleep mode yes no no yes yes auto xon/xoff flow yes no no yes no auto cts#/rts# flow yes no no yes yes auto dsr#/dtr# flow yes no no no no no. of rx interrupt thresholds 127 1 4 4 4 no. of tx interrupt thresholds 128 1 1 4 1 no. of flow control thresholds 128 n/a n/a 4 n/a transmitter empty interrupt yes no no no no readable status of flow control yes n/a no no no readable fifo levels yes n/a no no no clock prescaler options 248 n/a n/a 2 n/a rx/tx disable yes no no no no software reset yes no no no no device id yes no no no no 9-bit data frames yes no no no no rs485 buffer enable yes no no no no infra-red (irda) yes no no yes no table 1 ox16c950 performance compared with 16c450, 16c550, 16c650 and 16c750 devices improvements of the ox16c950 over previous generations of pc uart: deeper fifos: ox16c950 offers 128-byte deep fifos for the transmitter and receiver. higher data rates: transmission and reception baud rates up to 15mbps. a flexible clock prescaler offers division ratios of 1 to 31 7/8 in steps of 1/8 using a divide-by-?m n/8? circuitry. the flexible prescaler allows users to select from a wide variety of input clock frequencies as well as access to higher baud rates whilst maintaining compatibility with existing software drivers (see section 14.2). external clock options: the receiver can accept an ex ternal 1x clock on the dsr# input. the transmitter can accept a 1x clock on the ri# input and/or assert its own (nx) clock on the dtr# output. in 1x mode, asynchronous data may be transmitted and received at speeds up to 60mbps (see section 14.6). automatic flow control: the uart automatically handles either or both in-band (software) flow control (transmitting and receiving xon/xoff characters) and out-of-band (hardware) flow control using the rts#/cts# or dsr#/dtr# modem control lines. special character detection: the receiver can be programmed to generate an interrupt upon reception of a particular character value. power-down: the device can be placed in ?sleep mode? to conserve power. readable fifo levels: driver efficiency can be improved by using readable fifo levels. selectable trigger levels: the receiver fifo threshold can be arbitrarily programmed. the transmitter fifo threshold and thresholds for automatic flow control can be programmed to operate at a variety of trigger levels. additional control: the transmitter and receiver can be independently disabled.
data sheet revision 1.2 page 6 ox16c950 rev b oxford semiconductor ltd. additional status: software drivers are able to read the status of in-band and out-of-band automatic flow control, and distinguish between xoff and special character received interrupts. software reset: the software driver may reset the device to recover from unforeseen or unusual error conditions. transmitter empty interrupt: the transmitter can generate an interrupt when the fifo and shift register are both empty. rs485 buffer enable: the dtr# pin may be re-assigned as a buffer-enable signal for rs485 line driver in half-duplex mode (see acr[4:3] in section 15.3). device id: four bytes of device id are available to identify the ox16c950 device to software drivers. infra-red ?irda? interface: the uart contains an irda compliant modulator and demodulator. 9-bit data framing: the ox16c950 may be configured to use in 9-bit character framing for multi-drop protocols where a tag id (9 th bit) differentiates address and data characters. 2 b lock d iagram bus interface a[2:0] d[7:0] cs0 cs1 cs2# ior ior# iow iow# ads# control and dma interface fifosel reset rxrdy# txrdy# ddis modem control interface rts# dtr# out1 out2 cts# dsr# dcd# ri# clock & baud rate generator xtli xtlo clksel bdout# rclk interrupt control logic intsel int receiver sin transmitter sout 128 byte fifo 128 byte fifo internal data bus internal control bus control and status registers vdd gnd power supply figure 1: ox16c950 block diagram
data sheet revision 1.2 page 7 ox16c950 rev b oxford semiconductor ltd. 3 p in i nformation 44 pin plastic leaded chip carrier 48 pin thin quad flat pack db4 db3 db2 db1 db0 fifosel vdd ri# dcd# dsr# cts# 6543214443424140 db5 7 39 reset db6 8 38 out1# db7 9 37 dtr# rclk 10 36 rts# sin 11 35 out2# nc 12 34 intsel# sout 13 33 int cs0 14 32 rxrdy# cs1 15 31 a0 cs2# 16 30 a1 bdout# 17 29 a2 18 19 20 21 22 23 24 25 26 27 28 xtli xtlo iow# iow gnd clksel ior# ior ddis txrdy# ads# OX16C950-PCC60-B vsel db4 db3 db2 db1 db0 vdd ri# dcd# dsr# cts# fifosel 48 47 46 45 44 43 42 41 40 39 38 37 nc 1 36 intsel# db5 2 35 reset db6 3 34 out1# db7 4 33 dtr# rclk 5 32 rts# nc 6 31 out2# sin 7 30 int sout 8 29 rxrdy# cs0 9 28 a0 cs1 10 27 a1 cs2# 11 26 a2 bdout# 12 25 nc 13 14 15 16 17 18 19 20 21 22 23 24 nc xtli xtlo iow# iow gnd ior# ior clksel ddis txrdy# ads# ox16c950-tqc60-b
data sheet revision 1.2 page 8 ox16c950 rev b oxford semiconductor ltd. 4 p in d escriptions plcc tqfp dir 1 name description clock 18 14 i xtli crystal oscillator input or external clock pin. maximum frequency 60 mhz @ 5v, 50 mhz @ 3.3v 19 15 o xtlo crystal oscillator output. not used when an alternative ttl level clock is applied to xtli and can be left unconnected. 23 21 iu clksel the state of this pin on power up configures the internal clock prescaler. this pin has an internal pull-up. when clksel pin is high the pre-scalar is bypassed. connect this pin to gnd to enable the internal clock prescaler (see section 14.2). the complement of this pin is loaded in mcr[7] after a hardware reset. this pin can also be used as an altern ative external clock pin under software control (replacing xtli and thus reducing noise/power due to xtlo) for embedded applications processor interface 39 35 i reset active-high hardware reset. hardware reset is described in section 7.1. this pin must be tied inactive when not in use. 14, 15 9, 10 i cs0,cs1 active-high chip select. all chip select pins must be active for the device to be selected. 16 11 i cs2# active-low chip select. 29 -31 26 ? 28 i a[2:0] address lines to select channel registers. 28 24 i ads# active-low address strobe. when ads# signal is low, the address (a[2:0]) and chip select signal (cs0, cs1, cs2#) drive the internal logic, otherwise they are latched at the level they were when low-to-high transition of ads# signal occurred. this pin is used when address and chip selects are not stable during read or write cycles. if this functionality is not required, this pin can be permanently tied to gnd. 9 - 2 4 ? 2, 47 ? 43 i/o db[7:0] eight-bit 3-state data bus. 26 22 o ddis drive disable. this pin goes ac tive (high) when cpu is not reading from ox16c950. this signal can be used to disable an external transceiver. 20 21 16 17 i i iow# iow active-low write strobe. when iow# is used to write the chip, iow should be tied low (inactive). active-high write strobe. when iow is used to write the chip, iow# should be tied high (inactive). 24 25 19 20 i i ior# ior active-low read strobe. when ior# is used to read from the chip, ior should be tied low (inactive). active-high read strobe. when ior is used to read from the chip, ior# should be tied high (inactive).
data sheet revision 1.2 page 9 ox16c950 rev b oxford semiconductor ltd. plcc tqfp dir 1 name description serial port pins 13 8 o o sout irda_out transmitter serial data output. this pin is re-defined to irda output when irda mode is enabled, i.e. mcr[6] set in enhanced mode. 36 32 o rts# active-low request-to-send output. whenever the automated rts# flow control is enabled, the rts# pin is de-as serted and re-asserted if the receiver fifo reaches or falls below a pair of programmed flow control thresholds, respectively. this pin?s state is contro lled by bit 1 of the mcr. rts may also be used as a general-purpose output. 37 33 o o o dtr# 485_en tx_clk_out active-low modem data-terminal-ready output. whenever the automated dtr# flow control is enabled, the dtr# pin is asserted and de-asserted if the receiver fifo reaches or falls below a pair of programmed flow control thresholds, respectively. the state is set by bit 0 of the mcr. dtr may also be used as a general purpose output. in rs485 half-duplex mode, the dtr# pin may be programmed to reflect the state of the transmitter empty bit (or it?s inverse) to automatically control the direction of the rs485 transceiver buffer (see acr[4:3]). transmitter 1x (or baud rate generator output) clock. for isochronous applications, the 1x (or nx) transmitter clock may be asserted on the dtr# pin (see cks[5:4]). 11 7 i i sin irda_in receiver serial data input. this pin is re-defined to irda input when irda mode is enabled, i.e. mcr[6] set in enhanced mode. 40 38 i cts# active-low clear-to-send input. whenever the automated cts# flow control is enabled and the cts# pin is de-asserted, the transmitter will complete the current character and enter the idle mode until the cts# pin is re-asserted. however, flow control characters are tr ansmitted regardless of the state of the cts# pin. the state of this pin is reflected in bit 4 of the msr. it can also be used as a general-purpose input. 41 39 i i dsr# rx_clk_in active-low modem data-set-ready input. whenever the automated dsr# flow control is enabled and the dsr# pin is de-asserted, the transmitter will complete the current character and enter the idle mode until the dsr# pin is re-asserted. however, flow control characters are transmitted regardless of the state of the dsr# pin. the state of this pin is reflected in bit 5 of the msr. it can also be used as a genera- purpose input. external receiver clock for isochr onous applications. the rx_clk_in is selected when cks[1:0] = ?01?. 42 40 i dcd# active-low modem data-carrier-det ect input. the state of this pin is reflected in bit 7 of the msr. it can also be used as a general-purpose input 43 41 i i ri# tx_clk_in active-low modem ring-indicator input. the state of this pin is reflected in bit 6 of the msr. it can also be used as a general-purpose input. ri can be configured as tx and rx for a 1x clock in isochronous operation. external transmitter clock. this cloc k can be used by the transmitter (and by the receiver indirectly) when cks[6]=?1?. 17 12 o bdout# baud out. bdout# is a nx (usually 16x, see tcr) clock signal for the transmitter. it is the output of the baud generator module. the receiver can use this clock by connecting bdout# to the rclk pin or setting cks[1:0] to ?10? where bdout# will be connected to rclk internally. in this case setting cks[2] to ?1? will disable the bdout# pin to conserve power. 10 5 i rclk receiver clock. rclk is the nx (usually 16x, see tcr) baud rate clock for the receiver.
data sheet revision 1.2 page 10 ox16c950 rev b oxford semiconductor ltd. plcc tqfp dir 1 name description interrupt & dma pins 33 30 o int the serial channel has a three-state interrupt output. this signal goes active (high) when an interrupt condition occurs. the three-state logic is controlled by intsel# and mcr[3] as described below. 27 23 o txrdy# signal for dma transfer of transmitter data. there are two modes of dma signalling described in section 8.1. 32 29 o rxrdy# signal for dma transfer of received data. there are two modes of dma signalling described in section 8.1. 34 36 iu intsel# active-low interrupt select. this pin has an internal pull-up resistor. when intsel# is high or unconnected, the int pin is enabled and mcr[3] is ignored. when intsel# is low, the tri-state control of int is controlled by mcr[3]. in this case int is enabled when mcr[3] is set and is high- impedance when mcr[3] is low. this pin is used to save the external three-state buffer for the interrupt pin. when using this facility, the int output should be pulled down to gnd using a 1k ? resistor. miscellaneous pins 38 34 o out1# this user defined output pin reflects the complement of mcr[2]. it is inactive (high) after a hardware reset or during loopback mode. 35 31 o out2# this user defined output pin reflects the complement of mcr[3]. it is inactive (high) after a hardware reset or during loopback mode 1 37 id fifosel fifo select. this pin has an internal pull-down. for backward compatibility with 16c550, 16c650 and 16c750 devices the fifo depth is 16 when fifosel is low or left open. the fifo size is 128 when fifosel is high. the unlatched state of this pin is readable by software. the fifo size may be set to 128 by writing a 1 in fcr[5] when lcr[7] is set or by putting the device into enhanced mode, thus overri ding the state of the fifosel pin. this pin is unconnected in 16c550 and 16c750 devices. - 48 id vsel voltage selector. this pin is used to control the voltage thresholds on all input pins. when low (or unconnected), 5v biased ttl thresholds are used. when high, 3v biased ttl thresholds are used. generally should be tied high when the ox16c950 is being powered off 3 volts, and low (or unconnected) when powered off 5 volts. if tied high under 5v operation, cmos compatible input thresholds are obtained. as this pin is not accessible in the plcc, the plcc is unsuitable for 3v applications. 12 1, 13, 25, 6 nc these pins are not connected. power and ground 22 18 gnd ground (0 volts). the gnd pin should be tied to ground. 44 42 vdd power supply. the vdd pin should be tied to 5 volts or 3.3 volts table 2: pin descriptions note 1: direction key: i input iu input with pull-up id input with pull-down o output i/o bi-directional note: attention should be given to high frequency decoupling of power and ground pins due to the high frequency internal switch ing that occurs under normal operation
data sheet revision 1.2 page 11 ox16c950 rev b oxford semiconductor ltd. 4.1 further pin information pin description action when used action when not used bus interface pins cs0 chip select connect to active high chip select generation logic tie high ? all chip selects must be active in order to access the device cs1 chip select connect to active high chip select generation logic tie high ? all chip selects must be active in order to access the device cs2# chip select connect to active low chip select generation logic tie low ? all chip selects must be active in order to access the device ior additional i/o read control connect to processors active high i/o read line (and tie ior# high) tie low (ior# will be used to control i/o read operations) iow additional i/o write control connect to processors active high i/o write line (and tie iow# high) tie low (iow# will be used to control i/o read operations) control pins intsel# interrupt control mode tie low to allow software enable/disable of the interrupt pin. leave unconnected (pulled high internally to leave the interrupt pin permanently enabled). dma pins rxrdy# dma control signal output connect dire ct to dma control circuitry leave unconnected txrdy# dma control signal output connect dire ct to dma control circuitry leave unconnected clock related pins bdout# baud rate generator output connect direct to the rclk pin in order to run the receiver with the same clock as the transmitter leave unconnected rclk receiver clock input connect dire ctly to a suitable receiver clock source (usually the bdout# pin) n/a xtli crystal circuit input connect to suitable clock input n/a xtlo crystal circuit output connect to crystal oscillator circuit leave unconnected miscellaneous pins ddis driver disable output connect to active high bus transceiver drive disable (goes high when device is not being read from) leave unconnected ads# address strobe in connect direct to external control circuitry (low-high transition on this pin latches cs0-2 and a0-2) tie low out1# user defined output connect direct to ttl input of external circuit to control leave unconnected out2# user defined output connect direct to ttl input of external circuit to control leave unconnected common channel pins sout serial data output connect to a suitable line driver leave unconnected (serial data can not be transmitted) sin serial data input connect to a suitable line receiver leave unconnected (serial data can not be received) rts# request-to-send modem signal output connect to a suitable line driver leave unconnected cts# clear-to-send modem signal input connect to a suitable line receiver tie high dtr# data-terminal-ready modem signal output connect to a suitable line driver leave unconnected dsr# data-set-ready modem signal input connect to a suitable line receiver tie high
data sheet revision 1.2 page 12 ox16c950 rev b oxford semiconductor ltd. pin description action when used action when not used dcd# data-carrier-detect modem signal input connect to a suitable line receiver tie high ri# ring-indicator modem signal input connect to a suitable line receiver tie high int interrupt output connect to an available processor interrupt line leave unconnected (interrupts can not be used)
data sheet revision 1.2 page 13 ox16c950 rev b oxford semiconductor ltd. 5 m ode s election the ox16c950 device is a single channel device software compatible with the 16c450, 16c550, 16c654 and 16c750 uarts. the operation of the ox16c950 depends on a number of mode settings. these modes are referred to throughout this data sheet. the fifo depth and compatibility modes are tabulated below: uart mode fifo size fcr[0] enhanced mode (efr[4]=1) fcr[5] (guarded with lcr[7] = 1) fifosel pin 450 1 0 x x x 550 16 1 0 0 0 extended 550 128 1 0 x 1 650 128 1 1 x x 750 128 1 0 1 0 950* 128 1 1 x x table 3: uart mode configuration * note that 950 mode configuration is identical to 650 configuration 5.1 450 mode after a hardware reset bit 0 of the fifo control register (?fcr?) is cleared, hence ox16c950 is compatible with the 16c450. the transmitter and receiver fifos (referred to as the ?transmit holding register? and ?receiver holding register? respectively) have a depth of one. this is referred to as ?byte mode?. when fcr[0] is cleared, all other mode selection parameters are ignored. 5.2 550 mode connect fifosel to gnd or leave it unconnected. after a hardware reset, writing a 1 to fcr[0] will increase the fifo size to 16, providing compatibility with 16c550 devices. since this pin is a no-connect in 16c550 devices, replacing a 16c550 with ox16c950 would result in a 550 compatible device with 16 byte deep fifos. 5.3 extended 550 mode connect fifosel to vdd. writing a 1 to fcr[0] will now increase the fifo size to 128, thus providing a 550 device with 128 deep fifos. 5.4 750 mode for compatibility with 16c750, leave fifosel unconnected. writing a 1 to fcr[0] will increase the fifo size to 16. in a similar fashion to 16c750, the fifo size can be further increased to 128 by writing a 1 to fcr[5]. note that access to fcr[5] is protected by lcr[7]. i.e., to set fcr[5], software should first set lcr[7] to temporarily remove the guard. once fcr[5] is set, the software should clear lcr[7] for normal operation. the 16c750 additional features over the 16c550 are available as long as the uart is not put into enhanced mode (i.e. efr[4] should be ?0?). these features are: 1. deeper fifos 2. automatic rts/cts out-of-band flow control 3. sleep mode 5.5 650 mode the ox16c950 is compatible with the 16c650 when efr[4] is set, i.e. the devic e is in enhanced mode. as 650 software drivers usually put the device into enhanced mode, running 650 drivers on the ox16c950 device will result in 650 compatibility with 128 deep fifos, as long as fcr[0] is set. this is regardless of the state of the fifosel pin or package option. note that the 650 emulation mode of the ox16c950 provides 128 byte deep fifos whereas the standard 16c650 has only 32 byte fifos. 650 mode has the same enhancements as the 16c750 over the 16c550, but these are enabled using different registers. there are also additional enhancements over those of the 16c750 in this mode, these are: 1. automatic in-band flow control 2. special character detection 3. infra-red ?irda-format? transmit and receive mode 4. transmit trigger levels 5. optional clock prescaler
data sheet revision 1.2 page 14 ox16c950 rev b oxford semiconductor ltd. 5.6 950 mode the additional features offered in ox16c950 (950 mode) generally only apply when the uart is in enhanced mode (efr[4]=?1?). provided fcr[0] is set, in enhanced mode the fifo size is 128 regardless of the state of fifosel. note that 950 mode configuration is identical to that of 650 mode, however additional 950 specific features are enabled using the additional control register ?acr? (see section 15.3). in addition to larger fifos and higher baud rates, the enhancements of the 16c950 over the 16c654 are: ? selectable arbitrary trigger levels for the receiver and transmitter fifo interrupts ? improved automatic flow control using selectable arbitrary thresholds ? dsr#/dtr# automatic flow control ? transmitter and receiver can be optionally disabled ? software reset of device ? readable fifo fill levels ? optional generation of an rs-485 buffer enable signal ? four-byte device identification (0x16c95003) ? readable status for automatic in-band and out-of- band flow control ? external 1x clock modes (see section 14.4) ? flexible ?m n/8? clock prescaler (see section 14.2) ? programmable sample clock to allow data rates up to 15 mbps (see section 14.3) ? 9-bit data mode the 950 trigger levels are enabled when acr[5] is set (bits 4 to 7 of fcr are ignored). then arbitrary trigger levels can be defined in rtl, ttl, fcl and fch registers (see section 15). the additional status register (?asr?) offers flow control status for the local and remote transmitters. fifo levels are readable using rfl and tfl registers. the uart has a flexible prescaler capable of dividing the system clock by any value between 1 and 31.875 in steps of 0.125. it divides the system clock by an arbitrary value in ?m n/8? format, where m and n are 5 and 3-bit binary numbers programmed in cpr[7:3] and cpr[2:0] respectively. this arrangement offers a great deal of flexibility when choosing an input clock frequency to synthesize arbitrary baud rates. the default division value is 4 to provide backward compatibility with 16c650 devices. the user may apply an external 1x (or nx) clock for the transmitter and receiver to the ri# and dsr# pin respectively. the transmitter clock may be asserted on the dtr# pin. the external clock options are selected through the cks register (offset 0x02 of icr). it is also possible to define the over-sampling rate used by the transmitter and receiver clocks. the 16c450/16c550 and compatible devices employ 16 times over-sampling, i.e. there are 16 clock cycles per bit. however, ox16c950 can employ any over-sampling rate from 4 to 16 by programming the tcr register. this allows the data rates to be increased to 460.8 kbps using a 1.8432mhz clock, or 15 mbps using a 60 mhz clock. the default value after a reset for this register is 0x00, which corresponds to a 16 cycle sampling clock. writing 0x01, 0x02 or 0x03 will also result in a 16 cycle sampling clock. to program the value to any value from 4 to 15 it is necessary to write this value into tcr i.e. to set the device to a 13 cycle sampling clock it would be necessary to write 0x0d to tcr. for further information see sections 14.3. the ox16c950 also offers 9-bit data frames for multi-drop industrial applications.
data sheet revision 1.2 page 15 ox16c950 rev b oxford semiconductor ltd. 6 r egister d escription t ables the three address lines select the various registers in the uart. since there are more than 8 registers, selection of the regis ters is also dependent on the state of the line control register ?lcr? and additional control register ?acr?: 1. lcr[7]=1 enables the divider latch registers dll and dlm. 2. lcr specifies the data format used for both transmitter and receiver. writing 0xbf (an unused format) to lcr enables access to the 650 compatible register set. writing this value will set lcr[7] but leaves lcr[6:0] unchanged. therefore, the data format of the transmitter and receiver data is not affected. write the desired lcr value to exit from this selection. 3. acr[7]=1 enables access to the 950 specific registers. 4. acr[6]=1 enables access to the indexed control register set (icr) registers as described on page 17. register name address r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 thr 1 000 w data to be transmitted rhr 1 000 r data received ier 1,2 650/950 mode cts interrupt mask rts interrupt mask special char. detect 550/750 mode 001 r/w unused alternate sleep mode sleep mode modem interrupt mask rx stat interrupt mask thre interrupt mask rxrdy interrupt mask fcr 3 650 mode rhr trigger level thr trigger level 750 mode rhr trigger level fifo size unused 950 mode 010 w unused dma mode / tx trigger enable flush thr flush rhr enable fifo isr 3 010 r fifos enabled interrupt priority (enhanced mode) interrupt priority (all modes) interrupt pending lcr 4 011 r/w divisor latch access tx break force parity odd / even parity parity enable number of stop bits data length mcr 3,4 550/750 mode unused cts & rts flow control 650/950 mode 100 r/w baud prescale irda mode xon-any internal loop back enable out2 (int en) out1 rts dtr lsr 3,5 normal data error tx empty thr empty rx break framing error parity error overrun error rxrdy 9-bit data mode 101 r 9 th rx data bit msr 3 110 r dcd ri dsr cts delta dcd trailing ri edge delta dsr delta cts spr 3 normal temporary data storage register and indexed control regist er offset value bits 9-bit data mode 111 r/w unused 9 th tx data bit additional standard registers ? these registers requir e divisor latch access bit (lcr[7]) to be set to 1. dll 000 r/w divisor latch bits [7:0] (least significant byte) dlm 001 r/w divisor latch bits [1 5:8] (most significant byte) table 4: standard 550 compatible registers
data sheet revision 1.2 page 16 ox16c950 rev b oxford semiconductor ltd. register name address r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 to access these registers lcr must be set to 0xbf efr 010 r/w cts flow control rts flow control special char detect enhanced mode in-band flow control mode xon1 100 r/w xon character 1 9-bit mode special character 1 xon2 101 r/w xon character 2 9-bit mode special character 2 xoff1 110 r/w xoff character 1 9-bit mode special character 3 xoff2 111 r/w xoff character 2 9-bit mode special character 4 table 5: 650 compatible registers register name address r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 asr 1,6,7 001 r/w 7 tx idle fifo size fifo- sel special char detect dtr rts remote tx disabled tx disabled rfl 6 011 r number of characters in the receiver fifo tfl 3,6 100 r number of characters in the transmitter fifo icr 3,8,9 101 r/w data read/written depends on the value written to the spr prior to the access of t his register (see table 7 ) table 6: 950 specific registers register access notes: note 1: requires lcr[7] = 0 note 2: requires acr[7] = 0 note 3: requires that last value written to lcr was not 0xbf note 4: to read this register acr[7] must be = 0 note 5: to read this register acr[6] must be = 0 note 6: requires acr[7] = 1 note 7: only bits 0 and 1 of this register can be written note 8: to read this register acr[6] must be = 1 note 9: this register acts as a window through which to re ad and write registers in the indexed control register set
data sheet revision 1.2 page 17 ox16c950 rev b oxford semiconductor ltd. register name spr offset 10 r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 indexed control register set acr 0x00 r/w addit- ional status enable icr read enable 950 trigger level enable dtr definition and control auto dsr flow control enable tx disable rx disable cpr 0x01 r/w 5 bit ?integer? part of clock prescaler 3 bit ?fractional? part of clock prescaler tcr 0x02 r/w unused 4 bit n-times clock selection bits [3:0] cks 0x03 r/w tx 1x mode tx clk select bdout on dtr dtr 1x tx clk rx 1x mode disable bdout receiver clock sel[1:0] ttl 0x04 r/w unused transmitter interrupt trigger level (0-127) rtl 0x05 r/w unused receiver interrupt trigger level (1-127) fcl 0x06 r/w unused automatic flow control lower trigger level (0-127) fch 0x07 r/w unused automatic flow control higher trigger level (1-127) id1 0x08 r hardwired id byte 1 (0x16) id2 0x09 r hardwired id byte 1 (0xc9) id3 0x0a r hardwired id byte 1 (0x50) rev 0x0b r hardwired revision byte (0x03) csr 0x0c w writing 0x00 to this register will reset the uart (except the cks and cka registers) nmr 0x0d r/w unused 9 th bit schar 4 9 th bit schar 3 9 th bit schar 2 9 th bit schar 1 9 th -bit int. en. 9 bit enable mdm 0x0e r/w unused ? dcd wakeup disable trailing ri edge disable ? dsr wakeup disable ? cts wakeup disable rfc 0x0f r fcr[7] fcr[6] fcr[5] fcr[4] fcr[3] fcr[2] fcr[1] fcr[0] gds 0x10 r unused good data status dms 0x11 r/w force txrdy inactive force rxrdy inactive unused txrdy status ( r ) rxrdy status ( r ) pidx 0x12 r hardwired port index ( 0x00 ) cka 0x13 r/w unused output sys-clk on txrdy use clksel pin for sys-clk invert dtr signal invert internal tx clock invert internal rx clock table 7: indexed control register set note 10: the spr offset column indicate s the value that must be written into sp r prior to reading / writing any of the indexed control registers via icr. offset values not listed in the table are reserved for future use and must not be used. to read or write to any of the indexed control registers use the following procedure. writing to icr registers: ensure that the last value written to lcr was not 0xbf (reserved for 650 compatible register access value). write the desired offset to spr (address 111 2 ).
data sheet revision 1.2 page 18 ox16c950 rev b oxford semiconductor ltd. write the desired value to icr (address 101 2 ). reading from icr registers: ensure that the last value written to lcr was not 0xbf (see above). write 0x00 offset to spr to select acr. set bit 6 of acr (icr read enable) by writing x1xxxxxx 2 to address 101 2 . ensure that other bits in acr are not changed. (software drivers should keep a copy of the contents of t he acr elsewhere since reading icr involves overwriting acr!) write the desired offset to spr (address 111 2 ). read the desired value from icr (address 101 2 ). write 0x00 offset to spr to select acr. clear bit 6 of acr bye writing x0xxxxxx 2 to icr, thus enabling access to standard registers again.
data sheet revision 1.2 page 19 ox16c950 rev b oxford semiconductor ltd. 7 r eset c onfiguration 7.1 hardware reset after a hardware reset, all writable registers are reset to 0x00, with the following exceptions: 1. dll which is reset to 0x01. 2. mcr[7] is reset to the complement of the clksel input pin value (see section 11.1). 3. cpr is reset to 0x20. the state of read-only registers following a hardware reset is as follows: rhr[7:0]: indeterminate rfl[6:0]: 0000000 2 tfl[6:0]: 0000000 2 lsr[7:0]: 0x60 signifying that both the transmitter and the transmitter fifo are empty msr[3:0]: 0000 2 msr[7:4]: dependent on modem input lines dcd, ri, dsr and cts respectively isr[7:0]: 0x01, i.e. no interrupts are pending asr[7:0]: 1xx00000 2 rfc[7:0]: 00000000 2 gds[7:0]: 00000001 2 dms[7:0]: 00000010 2 cka[7:0]: 00000000 2 the reset state of output signals for are tabulated below: signal reset state sout inactive high rts# inactive high dtr# inactive high int inactive low when intsel# pin is high or floating, otherwise high-impedance rxrdy# inactive high txrdy# active low (thr is able to receive data). table 8: output signal reset state 7.2 software reset an additional feature available in the ox16c950 device is software resetting of the serial channel. the software reset is available using the csr register. software reset has the same effect as a hardware reset except it does not reset the clock source selections (i.e. cks register and cka register). to reset the uart write 0x00 to the channel software reset register ?csr?.
data sheet revision 1.2 page 20 ox16c950 rev b oxford semiconductor ltd. 8 t ransmitter & r eceiver fifo s both the transmitter and receiver have associated holding registers (fifos), referred to as the transmitter holding register (thr) and receiver holding register (rhr) respectively. in normal operation, when the transmitter finishes transmitting a byte it will remove the next data from the top of the thr and proceed to transmit it. if the thr is empty, it will wait until data is written into it. if thr is empty and the last character being transmitted has been completed (i.e. the transmitter shift register is empty) the transmitter is said to be idle. similarly, when the receiver finishes receiving a byte, it will transfer it to the bottom of the rhr. if the rhr is full, an overrun condition will occur (see section 9.3). data is written into the bottom of the thr queue and read from the top of the rhr queue completely asynchronously to the operation of the transmitter and receiver. the size of the fifos is dependent on the setting of the fcr register. when in byte mode, these fifos only accept one byte at a time before indicating that they are full; this is compatible with the 16c450. when in a fifo mode, the size of the fifos is either 16 (compatible with the 16c550) or 128. data written to the thr when it is full is lost. data read from the rhr when it is empty is invalid. the empty or full status of the fifos are indicated in the line status register ?lsr? (see section 9.3). interrupts can be generated or dma signals can be used to transfer data to/from the fifos. the number of items in each fifo may also be read back from the transmitter fifo level (tfl) and receiver fifo level (rfl) registers (see section 15.2). 8.1 fifo control register ?fcr? fcr[0]: enable fifo mode logic 0 ? byte mode. logic 1 ? fifo mode. this bit should be enabled before setting the fifo trigger levels. fcr[1]: flush rhr logic 0 ? no change. logic 1 ? flushes the contents of the rhr this is only operative when already in a fifo mode. the rhr is automatically flushed whenever changing between byte mode and a fifo mode. this bit will return to zero after clearing the fifos. fcr[2]: flush thr logic 0 ? no change. logic 1 ? flushes the contents of the thr, in the same manner as fcr[1] does for the rhr. dma transfer signalling: fcr[3]: dma signalling mode / tx trigger level enable logic 0 ? dma mode '0'. logic 1 ? dma mode '1'. note: in dma mode 0, the transmitter trigger level is always set to 1, thus ignoring fcr[5:4] and ttl. dma control signals can be generated using the txrdy# and rxrdy# pins. their operation is defined as follows: the txrdy# pin has no hysteres is and is simply activated using a comparison operation. when the uart is in dma mode 0 (or in byte mode), the txrdy# output pin is active (low) whenever thr is empty, otherwise it is inactive. when in dma mode 1, the txrdy# pin is inactive (high) when the thr is full, otherwise it is active, signifying that there is room in the transmit fifo. the rxrdy# pin can operate with hysteresis. in dma mode 0 (or in byte mode), rxrdy# is only active (low) when rhr contains data. when in dma mode 1 however, the operation is as follows: 1. rxrdy# is set active when rfl has reached the receiver interrupt trigger level or a time-out event has occurred (see section 10.3) it remains active as long as rhr is not empty. 2. rxrdy# is set inactive when rhr is empty. it remains in this state until condition 1 occurs. fcr[5:4]: thr trigger level generally in 450, 550, extended 550 and 950 modes these bits are unused (see section 5 for mode definition). in 650 mode they define the transmitter interrupt trigger levels and in 750 mode fcr[5] increases the fifo size. 450, 550 and extended 550 modes: the transmitter interrupt trigger levels are set to 1 and fcr[5:4] are ignored.
data sheet revision 1.2 page 21 ox16c950 rev b oxford semiconductor ltd. 650 mode: in 650 mode the transmitter interrupt trigger levels are set to the following values: fcr[5:4] transmit interrupt trigger level 00 16 01 32 10 64 11 112 table 9: transmit interrupt trigger levels these levels only apply when in enhanced mode and in dma mode 1 (fcr[3] = 1), otherwise the trigger level is set to 1. a transmitter empty interrupt will be generated (if enabled) if the tfl falls below the trigger level. 750 mode: in 750 compatible non-enhanced (efr[4]=0) mode, transmitter trigger level is set to 1, fcr[4] is unused and fcr[5] defines the fifo depth as follows: fcr[5]=0 transmitter and receiver fifo size is 16 bytes. fcr[5]=1 transmitter and receiver fifo size is 128 bytes. in non-enhanced mode and when fifosel pin is low, fcr[5] is only writable when lcr[7] is set. note that in enhanced mode, the fifo size is also increased to 128 bytes when fcr[0] is set. 950 mode: setting acr[5]=1 enables arbitrary transmitter trigger level setting using the ttl register (see section 15.4), hence fcr[5:4] are ignored. fcr[7:6]: rhr trigger level in 550, extended 550, 650 and 750 modes, the receiver fifo trigger levels are defined using fcr[7:6]. the interrupt trigger level and upper flow control trigger level where appropriate are defined by l2 in the table below. l1 defines the lower flow control trigger level where applicable. separate upper and lower flow control trigger levels introduce a hysteresis element in in-band and out-of- band flow control (see section 13). mode 650 fifo size 128 ext. 550 / 750 fifo size 128 550 fifo size 16 fcr [7:6] l1 l2 l1 l2 l1 l2 00 1 16 1 1 n/a 1 01 16 32 1 32 n/a 4 10 32 112 1 64 n/a 8 11 112 120 1 112 n/a 14 table 10: receiver trigger levels in byte mode (450 mode) the trigger levels are all set to 1. in all cases, a receiver data interrupt will be generated (if enabled) if the receiver fifo level (?rfl?) reaches the upper trigger level l2. 950 mode: when 950 trigger levels are enabled (acr[5]=1), more flexible trigger levels can be set by writing to the ttl, rtl, fcl and fch (see section 15) hence ignoring fcr[7:6]. 9 l ine c ontrol & s tatus 9.1 false start bit detection on the falling edge of a start bit, the receiver will wait for 1/2 bit and re-synchronise the receiver?s sampling clock onto the centre of the start bit. the start bit is valid if the sin line is still low at this mid-bit sample and the receiver will proceed to read in a data character. verifying the start bit prevents the receiver from assembling a false data character due to a low going noise spike on the sin input. once the first stop bit has been sampled, the received data is transferred to the rhr and the receiver will then wait for a low transition on sin signifying the next start bit. the receiver will continue receiving data even if the rhr is full or the receiver has been disabled (see section 15.3) in order to maintain framing synchronisation. the only difference is that the received data does not get transferred to the rhr. 9.2 line control register ?lcr? the lcr specifies the data format that is common to both transmitter and receiver. writing 0xbf to lcr enables access to the efr, xon1, xoff1, xon2 and xoff2, dll and dlm registers. this value (0xbf) corresponds to an unused data format. writing the value 0xbf to lcr will set lcr[7] but leaves lcr[6:0] unchanged. therefore, the data format of the transmitter and receiver data is not affected. write the desired lcr value to exit from this selection.
data sheet revision 1.2 page 22 ox16c950 rev b oxford semiconductor ltd. lcr[1:0]: data length lcr[1:0] determines the data length of serial characters. note however, that these values are ignored in 9-bit data framing mode, i.e. when nmr[0] is set. lcr[1:0] data length 00 5 bits 01 6 bits 10 7 bits 11 8 bits table 11: lcr data length configuration lcr[2]: number of stop bits lcr[2] defines the number of stop bits per serial character. lcr[2] data length no. stop bits 0 5,6,7,8 1 1 5 1.5 1 6,7,8 2 table 12: lcr stop bit number configuration lcr[5:3]: parity type the selected parity type will be generated during transmission and checked by the receiver, which may produce a parity error as a result. in 9-bit mode parity is disabled and lcr[5:3] is ignored. lcr[5:3] parity type xx0 no parity bit 001 odd parity bit 011 even parity bit 101 parity bit forced to 1 111 parity bit forced to 0 table 13: lcr parity configuration lcr[6]: transmission break logic 0 ? break transmission disabled. logic 1 ? forces the transmitter data output sout low to alert the communication terminal, or send zeros in irda mode. it is the responsibility of the software driver to ensure that the break duration is longer than the character period for it to be recognised remotely as a break rather than data. lcr[7]: divisor latch enable logic 0 ? access to dll and dlm registers disabled. logic 1 ? access to dll and dlm registers enabled. 9.3 line status register ?lsr? this register provides the status of data transfer to cpu. lsr[0]: rhr data available logic 0 ? rhr is empty: no data available logic 1 ? rhr is not empty: data is available to be read. lsr[1]: rhr overrun error logic 0 ? no overrun error. logic 1 ? data was received when the rhr was full. an overrun error has occurred. the error is flagged when the data would normally have been transferred to the rhr. lsr[2]: received data parity error logic 0 ? no parity error in normal mode or 9 th bit of received data is ?0? in 9-bit mode. logic 1 ? data has been received that did not have correct parity in normal mode or 9 th bit of received data is ?1? in 9-bit mode. the flag will be set when the data item in error is at the top of the rhr and cleared following a read of the lsr. in 9- bit mode lsr[2] is no longer a flag and corresponds to the 9 th bit of the received data in rhr. lsr[3]: received data framing error logic 0 ? no framing error. logic 1 ? data has been received with an invalid stop bit. this status bit is set and cleared in the same manner as lsr[2]. when a framing error occurs, the uart will try to re-synchronise by assuming that the error was due to sampling the start bit of the next data item. lsr[4]: received break error logic 0 ? no receiver break error. logic 1 ? the receiver received a break. a break condition occurs when the sin line goes low (normally signifying a start bit) and stays low throughout the start, data, parity and first stop bit. (note that the sin line is sampled at the bit rate). one zero character with associated break flag set will be transferred to the rhr and the receiver will then wait until the sin line returns high. the lsr[4] break flag will be set when this data item gets to the top of the rhr and it is cleared following a read of the lsr. lsr[5]: thr empty logic 0 ? transmitter fifo (thr) is not empty. logic 1 ? transmitter fifo (thr) is empty.
data sheet revision 1.2 page 23 ox16c950 rev b oxford semiconductor ltd. lsr[6]: transmitter and thr empty logic 0 ? the transmitter is not idle logic 1 ? thr is empty and the transmitter has completed the character in shift register and is in idle mode. (i.e. set whenever the transmitter shift register and the thr are both empty.) lsr[7]: receiver data error logic 0 ? either there are no receiver data errors in the fifo or it was cleared by an earlier read of lsr. logic 1 ? at least one parity error, framing error or break indication in the fifo. in 450 mode lsr[7] is permanently cleared, otherwise this bit will be set when an erroneous character is transferred from the receiver to the rhr. it is cleared when the lsr is read. note that in 16c550 this bit is only cleared when all of the erroneous data are removed from the fifo . in 9-bit data framing mode parity is permanently disabled, so this bit is not affected by lsr[2]. 10 i nterrupts & s leep m ode the serial channel interrupts are asserted on the int pin. when intsel# is high or unconnected, the int pin is forcing logic and mcr[3] is ignored. when intsel# is low, the tri-state control of int is controlled by mcr[3]. in this case the int pin is forcing when mcr[3] is set. it is in high- impedance state when mcr[3] is cleared. 10.1 interrupt enable register ?ier? serial channel interrupts are enabled using the interrupt enable register (?ier?). ier[0]: receiver data available interrupt mask logic 0 ? disable the receiver ready interrupt. logic 1 ? enable the receiver ready interrupt. ier[1]: transmitter empty interrupt mask logic 0 ? disable the transmitter empty interrupt. logic 1 ? enable the transmitter empty interrupt. ier[2]: receiver status interrupt normal mode: logic 0 ? disable the receiver status interrupt. logic 1 ? enable the receiver status interrupt. 9-bit data mode: logic 0 ? disable receiver status and address bit interrupt. logic 1 ? enable receiver status and address bit interrupt. in 9-bit mode (i.e. when nmr[0] is set) reception of a character with the address-bit (9 th bit) set can generate a level 1 interrupt if ier[2] is set. ier[3]: modem status interrupt mask logic 0 ? disable the modem status interrupt. logic 1 ? enable the modem status interrupt. ier[4]: sleep mode logic 0 ? disable sleep mode. logic 1 ? enable sleep mode whereby the internal clock of the channel is switched off. sleep mode is described in section 10.4. ier[5]: special character interrupt mask or alternate sleep mode 9-bit data framing mode: logic 0 ? disable the special character receive interrupt. logic 1 ? enable the special character receive interrupt. in 9-bit data mode, the receiver can detect up to four special characters programmed in special character 1 to 4. when ier[5] is set, a level 5 interrupt is asserted when a match is detected. 650/950 modes (non-9-bit data framing): logic 0 ? disable the special character receive interrupt. logic 1 ? enable the special character receive interrupt. in 16c650 compatible mode when the device is in enhanced mode (efr[4]=1), this bit enables the detection of special characters. it enables both the detection of xoff characters (when in-band flow control is enabled via efr[3:0]) and the detection of the xoff2 special character (when enabled via efr[5]). 750 mode (non-9-bit data framing): logic 0 ? disable alternate sleep mode. logic 1 ? enable alternate sleep mode whereby the internal clock of the channel is switched off. in 16c750 compatible mode (i.e. non-enhanced mode), this bit is used an alternate sleep mode and has the same effect as ier[4]. (see section 10.4)
data sheet revision 1.2 page 24 ox16c950 rev b oxford semiconductor ltd. ier[6]: rts interrupt mask logic 0 ? disable the rts interrupt. logic 1 ? enable the rts interrupt. this enable is only operative in enhanced mode (efr[4]=1). in non-enhanced mode, rts interrupt is permanently enabled. ier[7]: cts interrupt mask logic 0 ? disable the cts interrupt. logic 1 ? enable the cts interrupt. this enable is only operative in enhanced mode (efr[4]=1). in non-enhanced mode, cts interrupt is permanently enabled. 10.2 interrupt status register ?isr? the source of the highest priority interrupt pending is indicated by the contents of the interrupt status register ?isr?. there are nine sources of interrupt at six levels of priority (1 is the highest) as tabulated below: level interrupt source isr[5:0] see note 3 - no interrupt pending 1 000001 1 receiver status error or address-bit detected in 9-bit mode 000110 2a receiver data available 000100 2b receiver time-out 001100 3 transmitter thr empty 000010 4 modem status change 000000 5 2 in-band flow control xoff or special character (xoff2) or special character 1, 2, 3 or 4 or bit 9 set in 9-bit mode 010000 6 2 cts or rts change of state 100000 table 14: interrupt status identification codes note1: isr[0] indicates whet her any interrupts are pending. note2: interrupts of priority le vels 5 and 6 cannot occur unless the uart is in enhanced mode. note3: isr[5] is only used in 650 & 950 modes. in 750 mode, it is ?0? when fifo size is 16 and ?1? when fifo size is 128. in all other modes it is permanently set to ?0?. 10.3 interrupt description level 1: receiver status error interrupt (isr[5:0]=?000110?): normal (non-9-bit) mode: this interrupt is active whenever any of lsr[1], lsr[2], lsr[3] or lsr[4] are set. these flags are cleared following a read of the lsr. this interrupt is masked with ier[2]. 9-bit mode: this interrupt is active whenever any of lsr[1], lsr[2], lsr[3] or lsr[4] are set. the receiver error interrupt due to lsr[1], lsr[3] and lsr[4] is masked with ier[3]. the ?address-bit? received interrupt is masked with nmr[1]. the software driver can differentiate between receiver status error and received address-bit (9 th data bit) interrupt by examining lsr[1] and lsr[7]. in 9-bit mode lsr[7] is only set when lsr[3] or lsr[4] is set and it is not affected by lsr[2] (i.e. 9 th data bit). level 2a: receiver data available interrupt (isr[5:0]=?000100?): this interrupt is active whenever the receiver fifo level is above the interrupt trigger level. level 2b: receiver time-out interrupt (isr[5:0]=?001100?): a receiver time-out event, which may cause an interrupt, will occur when all of the following conditions are true: ? the uart is in a fifo mode ? there is data in the rhr. ? there has been no read of the rhr for a period of time greater than the time-out period. ? there has been no new data received and written into the rhr for a period of time greater than the time-out period. the time-out period is four times the character period (including start and stop bits) measured from the centre of the first stop bit of the last data item received. reading the first data item in rhr clears this interrupt. level 3: transmitter empty interrupt (isr[5:0]=?000010?): this interrupt is set when the transmit fifo level falls below the trigger level. it is cleared on an isr read of a level 3 interrupt or by writing more data to the thr so that the trigger level is exceeded. note that when 16c950 mode trigger levels are enabled (acr[5]=1) and the transmitter trigger level of zero is selected (ttl=0x00), a transmitter empty interrupt will only be asserted when both the transmitter fifo and transmitter shift register are empty and the sout line has returned to idle marking state.
data sheet revision 1.2 page 25 ox16c950 rev b oxford semiconductor ltd. level 4: modem change interrupt (isr[5:0]=?000000?): this interrupt is set by a modem change flag (msr[0], msr[1], msr[2] or msr[3]) becoming active due to changes in the input modem lines. this interrupt is cleared following a read of the msr. level 5: receiver in-band flow control (xoff) detect interrupt, receiver special character (xoff2) detect interrupt, receiver special character 1, 2, 3 or 4 interrupt or 9 th bit set interrupt in 9-bit mode (isr[5:0]=?010000?): a level 5 interrupt can only occur in enhanced-mode when any of the following conditions are met: ? a valid xoff character is received while in-band flow control is enabled. ? a received character matc hes xoff2 while special character detection is enabled. ? a received character matches special character 1, 2, 3 or 4 in 9-bit mode (see section 15.9). it is cleared on an isr read of a level 5 interrupt. level 6: cts or rts changed interrupt (isr[5:0]=?100000?): this interrupt is set whenever either of the cts# or rts# pins changes state from low to high. it is cleared on an isr read of a level 6 interrupt. 10.4 sleep mode for a channel to go into sleep mode, all of the following conditions must be met: ? sleep mode enabled (ier[4]=1 in 650/950 modes, or ier[5]=1 in 750 mode): ? the transmitter is idle, i.e. the transmitter shift register and fifo are both empty. ? sin is high. ? the receiver is idle. ? the receiver fifo is empty (lsr[0]=0). ? the uart is not in loopback mode (mcr[4]=0). ? changes on modem input lines have been acknowledged (i.e. msr[3:0]=0000). ? no interrupts are pending. a read of ier[4] (or ier[5] if a 1 was written to that bit instead) shows whether the power-down request was successful. the uart will fully retain its programmed state whilst in power-down mode. the channel will automatically exit power-down mode when any of the conditions 1 to 7 becomes false. it may be woken manually by clearing ier[4] (or ier[5] if the alternate sleep mode is enabled). sleep mode operation is not available in irda mode. 11 m odem i nterface 11.1 modem control register ?mcr? mcr[0]: dtr logic 0 ? force dtr# output to inactive (high). logic 1 ? force dtr# output to active (low). note that dtr# can be used for automatic out-of-band flow control when enabled using acr[4:3] (see section 15.3). mcr[1]: rts logic 0 ? force rts# output to inactive (high). logic 1 ? force rts# output to active (low). note that rts# can be used for automatic out-of-band flow control when enabled using efr[6] (see section 13.4). mcr[2]: out1 logic 0 ? force out1# output low when loopback mode is disabled. logic 1 ? force out1# output high. mcr[3]: out2/external interrupt enable logic 0 ? force out2# output low when loopback mode is disabled. if intsel# is low the external interrupt is in high-impedance state when mcr[3] is cleared. if intsel# is high mcr[3] does not affect the interrupt. logic 1 ? force out2# output high. if intsel# is low the external interrupt is enabled and operating in normal active (forcing) mode when mcr[3] is high. if intsel# is high mcr[3] does not affect the interrupt. mcr[4]: loopback mode logic 0 ? normal operating mode. logic 1 ? enable local loop-back mode (diagnostics). in local loop-back mode, the transmitter output (sout) and the four modem outputs (dtr#, rts#, out1# and out2#) are set in-active (high), and the receiver inputs sin, cts#, dsr#, dcd#, and ri# are all disabled. internally the transmitter output is connected to the receiver input and dtr#, rts#, out1# and out2# are connected to modem status inputs dsr#, cts#, ri# and dcd# respectively.
data sheet revision 1.2 page 26 ox16c950 rev b oxford semiconductor ltd. in this mode, the receiver and transmitter interrupts are fully operational. the modem control interrupts are also operational, but the interrupt sources are now the lower four bits of the modem control register instead of the four modem status inputs. the interrupts are still controlled by the ier. mcr[5]: enable xon-any in enhanced mode or enable out-of-band flow control in non-enhanced mode 650/950 modes (enhanced mode): logic 0 ? xon-any is disabled. logic 1 ? xon-any is enabled. in enhanced mode (efr[4]=1), this bit enables the xon- any operation. when xon-any is enabled, any received data will be accepted as a valid xon (see in-band flow control, section 13.3). 750 mode (non-enhanced mode): logic 0 ? cts/rts flow control disabled. logic 1 ? cts/rts flow control enabled. in non-enhanced mode, this bit enables the cts/rts out- of-band flow control. mcr[6]: irda mode logic 0 ? standard serial receiver and transmitter data format. logic 1 ? data will be transmitted and received in irda format. this function is only available in enhanced mode. it requires a 16x clock to function correctly. mcr[7]: baud rate prescaler select logic 0 ? normal (divide by 1) baud rate generator prescaler selected. logic 1 ? divide-by-?m n/8? baud rate generator prescaler selected. where m & n are programmed in cpr (icr offset 0x01). after a hardware reset, cpr defaults to 0x20 (divide-by-4) and mcr[7] is loaded with the complement of the clksel pin. user writes to this flag will only take effect in enhanced mode. see section 13.1. 11.2 modem status register ?msr? msr[0]: delta cts# indicates that the cts# input has changed since the last time the msr was read. msr[1]: delta dsr# indicates that the dsr# input has changed since the last time the msr was read. msr[2]: trailing edge ri# indicates that the ri# input has changed from low to high since the last time the msr was read. msr[3]: delta dcd# indicates that the dcd# input has changed since the last time the msr was read. msr[4]: cts this bit is the complement of the cts# input. it is equivalent to rts (mcr[1]) during internal loop-back mode. msr[5]: dsr this bit is the complement of the dsr# input. it is equivalent to dtr (mcr[0]) during internal loop-back mode. msr[6]: ri this bit is the complement of the ri# input. in internal loop- back mode it is equivalent to the internal out1. msr[7]: dcd this bit is the complement of the dcd# input. in internal loop-back mode it is equivalent to the internal out2.
data sheet revision 1.2 page 27 ox16c950 rev b oxford semiconductor ltd. 12 o ther s tandard r egisters 12.1 divisor latch registers ?dll & dlm? the divisor latch registers are used to program the baud rate divisor. this is a value between 1 and 65535 by which the input clock is divided by in order to generate serial baud rates. after a hardware reset, the baud rate used by the transmitter and receiver is given by: divisor inputclock baudrate * 16 = where divisor is given by dll + ( 256 x dlm ). more flexible baud rate generation options are also available. see section 14 for full details. 12.2 scratch pad register ?spr? the scratch pad register does not affect operation of the rest of the uart in any way and can be used for temporary data storage. the register may also be used to define an offset value to access the registers in the indexed control register set. for more information on indexed control registers see table 7 and section 15.
data sheet revision 1.2 page 28 ox16c950 rev b oxford semiconductor ltd. 13 a utomatic f low c ontrol automatic in-band flow control, automatic out-of-band flow control and special characte r detection features can be used when in enhanced mode and are software compatible with the 16c654. alternatively, 16c750 compatible automatic out-of-band flow control can be enabled when in non-enhanced mode. in 950 mode, in-band and out-of- band flow controls are compatible with 16c654, with the addition of fully programmable flow control thresholds. 13.1 enhanced features register ?efr? writing 0xbf to lcr enables access to the efr and other enhanced mode registers. this value corresponds to an unused data format. writing 0xbf to lcr will set lcr[7] but leaves lcr[6:0] unchanged. therefore, the data format of the transmitter and receiver data is not affected. write the desired lcr value to exit from this selection. note: in-band transmit and receive flow control is disabled in 9-bit mode. efr[1:0]: in-band receive flow control mode when in-band receive flow control is enabled, the uart compares the received data with the programmed xoff character. when this occurs, the uart will disable transmission as soon as any current character transmission is complete. the uart then compares the received data with the programmed xon character. when a match occurs, the uart will re-enable transmission (see section 15.6). for automatic in-band flow control, bit 4 of efr must be set. the combinations of software receive flow control can be selected by programming efr[1:0] as follows: logic [00] ? in-band receive flow control is disabled. logic [01] ? single character in-band receive flow control enabled, recognising xon2 as the xon character and xoff2 as the xoff character. logic [10] ? single character in-band receive flow control enabled, recognising xon1 as the xon character and xoff1 and the xoff character. logic [11] ? the behavior of the receive flow control is dependent on the configuration of efr[3:2]. single character in-band receive flow control is enabled, accepting both xon1 and xon2 as valid xon characters and both xoff1 and xoff2 as valid xoff characters when efr[3:2] = ?01? or ?10?. efr[1:0] should not be set to ?11? when efr[3:2] is either ?00?. efr[3:2]: in-band transmit flow control mode when in-band transmit flow control is enabled, an xon/xoff character is inserted into the data stream whenever the rfl passes the upper trigger level and falls below the lower trigger level respectively. for automatic in-band flow control, bit 4 of efr must be set. the combinations of software transmit flow control can then be selected by programming efr[3:2] as follows: logic [00] ? in-band transmit flow control is disabled. logic [01] ? single character in-band transmit flow control enabled, using xon2 as the xon character and xoff2 as the xoff character. logic [10] ? single character in-band transmit flow control enabled, using xon1 as the xon character and xoff1 as the xoff character. logic[11] ? the value efr[3:2] = ?11? is reserved for future use and should not be used efr[4]: enhanced mode logic 0 ? non-enhanced mode. disables ier bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7 and in-band flow control. whenever this bit is cleared, the setting of other bits of efr are ignored. logic 1 ? enhanced mode. enables the enhanced mode functions. these functions include enabling ier bits 4-7, fcr bits 4-5, mcr bits 5-7. for in-band flow control the software driver must set this bit first. if this bit is set, out-of-band flow control is configured with efr bits 6-7, otherwise out-of-band flow control is compatible with 16c750. efr[5]: enable special character detection logic 0 ? special character detection is disabled. logic 1 ? while in enhanced mode (efr[4]=1), the uart compares the incoming receiver data with the xoff2 value. upon a correct match, the received data will be transferred to the rhr and a level 5 interrupt (xoff or special character) will be asserted if level 5 interrupts are enabled (ier[5] set to 1).
data sheet revision 1.2 page 29 ox16c950 rev b oxford semiconductor ltd. efr[6]: enable automatic rts flow control. logic 0 ? rts flow control is disabled (default). logic 1 ? rts flow control is enabled in enhanced mode (i.e. efr[4] = 1), where the rts# pin will be forced inactive high if the rfl reaches the upper flow control threshold. this will be released when the rfl drops below the lower threshold. the 650 and 950 software drivers should use this bit to enable rts flow control. the 750 compatible driver uses mcr[5] to enable rts flow control. efr[7]: enable automatic cts flow control. logic 0 ? cts flow control is disabled (default). logic 1 ? cts flow control is enabled in enhanced mode (i.e. efr[4] = 1), where the data transmission is prevented whenever the cts# pin is held inactive high. the 650 and 950 software drivers should use this bit to enable cts flow control. the 750 compatible driver uses mcr[5] to enable cts flow control. 13.2 special character detection in enhanced mode (efr[4]=1), when special character detection is enabled (efr[5]=1) and the receiver matches received data with xoff2, the 'r eceived special character' flag asr[4] will be set and a level 5 interrupt is asserted, (if enabled by ier[5]). this flag will be cleared following a read of asr. the received status (i.e. parity and framing) of special characters does not have to be valid for these characters to be accepted as valid matches. 13.3 automatic in-band flow control when in-band receive flow control is enabled, the uart will compare the received data with xoff1 or xoff2 characters to detect an xoff c ondition. when this occurs, the uart will disable transmiss ion as soon as any current character transmission is complete. status bits isr[4] and asr[0] will be set. a level 5 interrupt will occur if enabled by ier[5]. the uart will then compare all received data with xon1 or xon2 characters to detect an xon condition. when this occurs, the uart will re-enable transmission and status bits isr[4] and asr[0] will be cleared. any valid xon/xoff characters will not be written into the rhr. an exception to this rule occurs if special character detection is enabled and an xoff2 character is received that is a valid xoff. in this instance, the character will be written into the rhr. the received status (i.e. parity and framing) of xon/xoff characters does not have to be va lid for these characters to be accepted as valid matches. when the 'xon any' flag (mcr[5]) is set, any received character is accepted as a valid xon condition and the transmitter will be re-enabled. the received data will be transferred to the rhr. when in-band transmit flow control is enabled, the rfl will be sampled whenever the transmitter is idle (briefly, between characters, or when the thr is empty) and an xon/xoff character may be inserted into the data stream if needed. initially, remote transmissions are enabled and hence asr[1] is clear. if asr[1] is clear and the rfl has passed the upper trigger level (i.e. is above the trigger level), xoff will be sent and asr[1] will be set. if asr[1] is set and the rfl falls below the lower trigger level, xon will be sent and asr[1] will be cleared. if transmit flow control is disabled after an xoff has been sent, an xon will be sent automatically. 13.4 automatic out-of-band flow control automatic rts/cts flow control is selected by different means, depending on whether the uart is in enhanced or non-enhanced mode. when in non-enhanced mode, mcr[5] enables both rts and cts flow control. when in enhanced mode, efr[6] enables automatic rts flow control and efr[7] enables automatic cts flow control. this allows software compatibility with both 16c650 and 16c750 drivers. when automatic cts flow control is enabled and the cts# input becomes active, the ua rt will disable transmission as soon as any current characte r transmission is complete. transmission is resumed whenever the cts# input becomes inactive. when automatic rts flow control is enabled, the rts# pin will be forced inactive when the rfl reaches the upper trigger level and will return to active when the rfl falls below the lower trigger level. the automatic rts# flow control is anded with mcr[1] and hence is only operational when mcr[1]=1. this allows the software driver to override the automatic flow control and disable the remote transmitter regardless by setting mcr[1]=0 at any time. automatic dtr/dsr flow control behaves in the same manner as rts/cts flow control but is enabled by acr[3:2], regardless of whether or not the uart is in enhanced mode.
data sheet revision 1.2 page 30 ox16c950 rev b oxford semiconductor ltd. 14 b aud r ate g eneration 14.1 general operation the uart contains a programmable baud rate generator that is capable of taking any clock input from dc to 60mhz (at 5v) and dividing it by any 16-bit divisor number from 1 to 65535 written into the dlm (msb) and dll (lsb) registers. in addition to this, a clock prescaler register is provided which can further divide the clock by values in the range 1.0 to 31.875 in steps of 0.125. also, a further feature is the times clock register ?tcr? which allows the sampling clock to be set to any value between 4 and 16. these clock options allow for highly flexible baud rate generation capabilities from almost any input clock frequency (up to 60mhz). the actual transmitter and receiver baud rate is calculated as follows: prescaler divisor sc inputclock baudrate * * = where : sc = sample clock values defined in tcr[3:0] divisor = dll + ( 256 x dlm ) prescaler = 1 when mcr[7] = ?0? else: = m + ( n / 8 ) where: m = cpr[7:3] (integer part ? 1 to 31) n = cpr[2:0] (fractional part ? 0.000 to 0.875 ) see next section for a discussion of the clock prescaler and times clock register. after a hardware reset, the prescaler is bypassed (set to 1) and tcr is set to 0x00 (i.e. sc = 16). assuming this default configuration, the follow ing table gives the divisors required to be programmed into the dll and dlm registers in order to obtain various standard baud rates: dlm:dll divisor word baud rate (bits per second) 0x0900 50 0x0300 110 0x0180 300 0x00c0 600 0x0060 1,200 0x0030 2,400 0x0018 4,800 0x000c 9,600 0x0006 19,200 0x0004 28,800 0x0003 38,400 0x0002 57,600 0x0001 115,200 table 15: standard pc com port baud rate divisors (assuming a 1.8432mhz crystal)
data sheet revision 1.2 page 31 ox16c950 rev b oxford semiconductor ltd. 14.2 clock prescaler register ?cpr? the cpr register is located at offset 0x01 of the icr the prescaler divides the system clock by any value in the range of 1 to ?31 7/8? in steps of 1/8. the divisor takes the form ?m + n/8?, where m is the 5 bit value defined in cpr[7:3] and n is the 3 bit value defined in cpr[2:0]. the prescaler is by-passed and a prescaler value of ?1? is selected by default when mcr[7] = 0. mcr[7] is set to the complement of clksel pin after a hardware reset but may be overwritten by software. note however that since access to mcr[7] is restricted to enhanced mode only, efr[4] should first be set and then mcr[7] set or cleared as required. if clksel is connected to ground or mcr[7] is set by software, the internal clock prescaler is enabled. upon a hardware reset, cpr defaults to 0x20 (division-by- 4). compatibility with existing 16c550 baud rate divisors is maintained using either a 1.8432mhz clock with clksel pin connected to vdd, or a 7.372mhz clock with clksel connected to gnd. in the latter case, clearing mcr[7] would bypass the prescaler and hence quadruple all selected baud rates (providing a maximum of 460.8kbps as opposed to 115.2kbps) for higher baud rates use a higher frequency clock, e.g. 14.7456mhz, 18.432mhz, 32mhz, 40mhz or 60.0mhz. the flexible prescaler allows system designers to generate popular baud rates using clocks that are not integer multiples of the required rate. when using a non-standard clock frequency, compatibility with existing 16c550 software drivers may be maintained with a minor software patch to program the on-board prescaler to divide the high frequency clock down to 1.8432mhz. table 17 on the following page gives the prescaler values required to operate the uarts at compatible baud rates with various different crystal frequencies. also given is the maximum available baud rates in tcr = 16 and tcr = 4 modes with cpr = 1. 14.3 times clock register ?tcr? the tcr register is located at offset 0x02 of the icr the 16c550 and other compatible devices such as 16c650 and 16c750 use a 16 times (16x) over-sampling channel clock. the 16x over-sampling clock means that the channel clock runs at 16 times the selected serial bit rate. it limits the highest baud rate to 1/16 of the system clock when using a divisor latch value of unity. however, the 16c950 uart is designed in a manner to enable it to accept other multiplications of the bit rate clock. it can use values from 4x to 16x clock as programmed in the tcr as long as the clock (oscillator) frequency error, stability and jitter are within reasonable parameters. upon hardware reset the tcr is reset to 0x00 which means that a 16x clock will be used, for compatibility with the 16c550 and compatibles. the maximum baud-rates available for various system clock frequencies at all of the allowable values of tcr are indicated in table 18 on the following page. these are the values in bits-per-second (bps) that are obtained if the divisor latch = 0x01 and the prescaler is set to 1. the ox16c950 has the facility to operate at baud-rates up to 15 mbps at 5v. the table below indicates how the value in the register corresponds to the number of clock cycles per bit. tcr[3:0] is used to program the clock. tcr[7:4] are unused and will return ?0000? if read. tcr[3:0] clock cycles per bit 0000 to 0011 16 0100 to 1111 4-15 table 16: tcr sample clock configuration the use of tcr does not require the device to be in 650 or 950 mode although only drivers that have been written to take advantage of the 950 mode features will be able to access this register. writing 0x01 to the tcr will not switch the device into 1x isochronous mode, this is explained in the following section. (tcr has no effect in isochronous mode). if 0x01, 0x10 or 0x11 is written to tcr the device will operate in 16x mode. reading tcr will always return the last value that was written to it irrespective of mode of operation.
data sheet revision 1.2 page 32 ox16c950 rev b oxford semiconductor ltd. clock frequency (mhz) cpr value effective crystal frequency error from 1.8432mhz (%) max. baud rate with cpr = 1, tcr = 16 max. baud rate with cpr = 1, tcr = 4 1.8432 0x08 (1.000) 1.8432 0.00 115,200 460,800 7.3728 0x20(4.000) 1.8432 0.00 460,800 1,843,200 14.7456 0x80 (8.000) 1.8432 0.00 921,600 3,686,400 18.432 0x50 (10.000) 1.8432 0.00 1,152,000 4,608,000 32.000 0x8b(17.375) 1.8417 0.08 2,000,000 8,000,000 33.000 0x8f (17.875) 1.8462 0.16 2,062,500 8,250,000 40.000 0xae (21.750) 1.8391 0.22 2,500,000 10,000,000 50.000 0xd9 (27.125) 1.8433 0.01 3,125,000 12,500,000 60.000* 0xff (31.875) 1.8824 2.13 3,750,000 15,000,000 table 17: example clock options and their assosiacted maximum baud rates system clock (mhz) sampling clock tcr value 1.8432 7.372 14.7456 18.432 32 40 50 60 16 0x00 115,200 460,750 921,600 1.152m 2.00m 2.50m 3.125m 3.75m 15 0x0f 122,880 491,467 983,040 1,228,800 2,133,333 2,666,667 3,333,333 4.00m 14 0x0e 131,657 526,571 1,053,257 1,316,571 2,285,714 2,857,143 3,571,429 4,285,714 13 0x0d 141,785 567,077 1,134,277 1,417,846 2,461,538 3,076,923 3,846,154 4,615,384 12 0x0c 153,600 614,333 1,228,800 1,536,000 2,666,667 3,333,333 4,166,667 5.00m 11 0x0b 167,564 670,182 1,340,509 1,675,636 2,909,091 3,636,364 4,545,455 5,454545 10 0x0a 184,320 737,200 1,474,560 1,843,200 3.20m 4.00m 5.00m 6.00m 9 0x09 204,800 819,111 1,638,400 2,048,000 3,555,556 4,444,444 5,555,556 6,666,667 8 0x08 230,400 921,500 1,843,200 2,304,000 4.00m 5.00m 6.25m 7.50m 7 0x07 263,314 1,053,143 2,106,514 2,633,143 4,571,429 5,714,286 7,142,857 8,571428 6 0x06 307,200 1,228,667 2,457,600 3,072,000 5,333,333 6,666,667 8,333,333 10.00m 5 0x05 368,640 1,474,400 2,949,120 3,686,400 6.40m 8.00m 10.00m 12.00m 4 0x04 460,800 1,843,000 3,686,400 4,608,000 8.00m 10.00m 12.50m 15.00m table 18: maximum baud rates available at all ?tcr? sampling clock values
data sheet revision 1.2 page 33 ox16c950 rev b oxford semiconductor ltd. 14.4 input clock options a system clock must be applied to xtli pin on the device (or clksel if selected by software). the speed of this clock determines the maximum baud rate at which the device can receive and transmit serial data. this maximum is equal to one sixteenth of the frequency of the system clock (increasing to one quarter of this value if tcr=4 is used). the industry standard system clock for pc com ports is 1.8432 mhz, limiting the maximum baud rate to 115.2 kbps. the ox16c95x uarts support system clocks up to 50mhz (60mhz for the ox16c950 at 5v) and its flexible baud rate generation hardware means that almost any frequency can be optionally scaled down for compatibility with standard devices. designers have the option of using either ttl clock modules or crystal oscillator ci rcuits for system clock input, with minimal additional components. the following two sections describe how each can be connected. 14.5 ttl clock module using a ttl module for the sy stem clock simply requires the module to be supplied with +5v power and gnd connections. the clock output can then be connected directly to xtli. xtlo should be left unconnected. clock xtli vdd figure 2: ttl clock module connectivity 14.6 external 1x clock mode the transmitter and receiver c an accept an external clock applied to the ri# and dsr# pins respectively. the clock options are selected using the clock select register (cks - see section 15.8). the transmitter and receiver may be configured to operate in 1x (isochronous) mode by setting cks[7] and cks[3], respectively. in isochronous mode, transmitter or receiver will use the 1x clock (usually but not necessarily an external s ource) where asynchronous framing is maintained using start, parity and stop-bits. however serial transmission and reception is synchronised to the 1x clock. in this mode asynchronous data may be transmitted at baud rates up to 60mbps. the local 1x clock source can be asserted on the dtr# pin. note that line drivers need to be capable of transmission at data rates twice the system clock used (as one cycle of the system clock corresponds to 1 bit of serial data). also note that enabling modem interrupts is illegal in isochronous mode, as the clock signal will cause a continuous change to the modem status (unless masked in mdm register, see section 15.10). 14.7 crystal oscillator circuit the ox16c950 may be clocked by a crystal connected to xtli and xtlo or directly from a clock source connected to the xtli pin (or clksel if selected by software). the circuit required to use the on-chip oscillator is shown opposite. r 1 r 2 c 1 c 2 xtli xtlo figure 3: crystal oscillator circuit frequency range (mhz) c1 (pf) c2 (pf) r1 ( ? ) r2 ( ? ) 1.8432 ? 8 68 22 220k 470r 8-60 33-68 33 ? 68 220k-2m2 470r table 19: component values note: for better stability use a smaller value of r 1 . increase r 1 to reduce power consumption. the total capacitive load (c1 in series with c2) should be that specified by the crystal manufacturer (nominally 16pf)
data sheet revision 1.2 page 34 ox16c950 rev b oxford semiconductor ltd. 15 a dditional f eatures 15.1 additional status register ?asr? asr[0]: transmitter disabled logic 0 ? the transmitter is not disabled by in-band flow control. logic 1 ? the receiver has detected an xoff, and has disabled the transmitter. this bit is cleared after a hardware reset or channel software reset. the software driver may write a 0 to this bit to re-enable the transmitter if it was disabled by in-band flow control. writing a 1 to this bit has no effect. asr[1]: remote transmitter disabled logic 0 ? the remote transmitter is not disabled by in- band flow control. logic 1 ? the transmitter has sent an xoff character, to disable the remote transmitter. (cleared when a subsequent xon is sent). this bit is cleared after a hardware reset or channel software reset. the software driver may write a 0 to this bit to re-enable the remote transmitter (an xon is transmitted). writing a 1 to this bit has no effect. note : the remaining bits (asr[7:2]) of this register are read only asr[2]: rts this is the complement of the actual state of the rts# pin when the device is not in loopback mode. the driver software can determine if the remote transmitter is disabled by rts# out-of-band flow control by reading this bit. in loopback mode this bit reflects the flow control status rather than the pin?s actual state. asr[3]: dtr this is the complement of the actual state of the dtr# pin when the device is not in loopback mode. the driver software can determine if the remote transmitter is disabled by dtr# out-of-band flow control by reading this bit. in loopback mode this bit reflects the flow control status rather than the pin?s actual state. asr[4]: special character detected logic 0 ? no special character has been detected. logic 1 ? a special character has been received and is stored in the rhr. this can be used to determine whether a level 5 interrupt was caused by receiving a spec ial character rather than an xoff. the flag is cleared following the read of the asr. asr[5]: fifosel this bit reflects the unlatched state of the fifosel pin. asr[6]: fifo size logic 0 ? fifos are 16 deep if fcr[0] = 1. logic 1 ? fifos are 128 deep if fcr[0] = 1. note: if fcr[0] = 0, the fifos are 1 deep. asr[7]: transmitter idle logic 0 ? transmitter is transmitting. logic 1 ? transmitter is idle. this bit reflects the state of the internal transmitter. it is set when both the transmitter fifo and shift register are empty. 15.2 fifo fill levels ?tfl & rfl? the number of characters stored in the thr and rhr can be determined by reading the tfl and rfl registers respectively. as the uart clock is asynchronous with respect to the processor, it is possible for the levels to change during a read of these fifo levels. it is therefore recommended that the levels are read twice and compared to check that the values obtained are valid. the values should be interpreted as follows: 1. the number of characters in the thr is no greater than the value read back from tfl. 2. the number of characters in the rhr is no less than the value read back from rfl. 15.3 additional control register ?acr? the acr register is located at offset 0x00 of the icr acr[0]: receiver disable logic 0 ? the receiver is enabled, receiving data and storing it in the rhr. logic 1 ? the receiver is disabled. the receiver continues to operate as normal to maintain the framing synchronisation with the receive data stream but received data is not stored into the rhr. in-band flow control characters continue to be detected and acted upon. special characters will not be detected. changes to this bit will only be recognised following the completion of any data reception pending.
data sheet revision 1.2 page 35 ox16c950 rev b oxford semiconductor ltd. acr[1]: transmitter disable logic 0 ? the transmitter is enabled, transmitting any data in the thr. logic 1 ? the transmitter is disabled. any data in the thr is not transmitted but is held. however, in-band flow control characters may still be transmitted. changes to this bit will only be recognised following the completion of any data transmission pending. acr[2]: enable automatic dsr flow control logic 0 ? normal. the state of the dsr# line does not affect the flow control. logic 1 ? data transmission is prevented whenever the dsr# pin is held inactive high. this bit provides another automatic out-of-band flow control facility using the dsr# line. acr[4:3]: dtr# line configuration when bits 4 or 5 of cks (offset 0x03 of icr) are set, the transmitter 1x clock or the output of the baud rate generator (nx clock) are asserted on the dtr# pin, otherwise the dtr# pin is defined as follows: logic [00] ? dtr# is compatible with 16c450, 16c550, 16c650 and 16c750 (i.e. normal). logic [01] ? dtr# pin is used for out-of-band flow control. it will be forced inactive high if the receiver fifo level (?rfl?) reaches the upper flow control threshold. dtr# line will be re-activated when the rfl drops below the lower threshold (see fcl & fch). logic [10] ? dtr# pin is configured to drive the active low enable pin of an external rs485 buffer. in this configuration the dtr# pin will be forced low whenever the transmitter is not empty (lsr[6]=0), otherwise dtr# pin is high. logic [11] ? dtr# pin is configured to drive the active- high enable pin of an external rs485 buffer. in this configuration, the dtr# pin will be forced high whenever the transmitter is not empty (lsr[6]=0), otherwise dtr# pin is low. if the user sets acr[4], then the dtr# line is controlled by the status of the transmitter empty bit of lcr. when acr[4] is set, acr[3] is used to select active high or active low enable signals. in half-duplex systems using rs485 protocol, this facility enables the dtr# line to directly control the enable signal of external 3-state line driver buffers. when the transmitter is empty the dtr# would go inactive once the sout line returns to it?s idle marking state. acr[5]: 950 mode trigger levels enable logic 0 ? interrupts and flow control trigger levels are as described in fcr register and are compatible with 16c650/16c750 modes. logic 1 ? 16c950 specific enhanced interrupt and flow control trigger levels defined by rtl, ttl, fcl and fch are enabled. acr[6]: icr read enable logic 0 ? the line status register is readable. logic 1 ? the indexed control registers are readable. setting this bit will map the icr set to the lsr location for reads. during normal operation this bit should be cleared. acr[7]: additional status enable logic 0 ? access to the asr, tfl and rfl registers is disabled. logic 1 ? access to the asr, tfl and rfl registers is enabled. when acr[7] is set, the mcr and lcr registers are no longer readable but remain writable, and the tfl and rfl registers replace them in the memory map for read operations. the ier register is replaced by the asr register for all operations. the software driver may leave this bit set during normal operation, since mcr, lcr and ier do not generally need to be read.
data sheet revision 1.2 page 36 ox16c950 rev b oxford semiconductor ltd. 15.4 transmitter trigger level ?ttl? the ttl register is located at offset 0x04 of the icr whenever 950 trigger levels ar e enabled (acr[5]=1), bits 4 and 5 of fcr are ignored and an alternative arbitrary transmitter interrupt trigger level can be defined in the ttl register. this 7-bit value provides a fully programmable transmitter interrupt trigger facility. in 950 mode, a priority level 3 interrupt occurs indicating that the transmitter buffer requires more characters w hen the interrupt is not masked (ier[1]=1) and the transmitter fifo level falls below the value stored in the ttl register. the value 0 (0x00) has a special meaning. in 950 mode when the user writes 0x00 to the ttl register, a level 3 interrupt only occurs when the fifo and the transmitter shift register are both empty and the sout line is in the idle marking state. this feature is particularly useful to report back the empty state of the transmitter after its fifo has been flushed away. 15.5 receiver interrupt. trigger level ?rtl? the rtl register is located at offset 0x05 of the icr whenever 950 trigger levels ar e enabled (acr[5]=1), bits 6 and 7 of fcr are ignored and an alternative arbitrary receiver interrupt trigger level can be defined in the rtl register. this 7-bit value provides a fully programmable receiver interrupt trigger facility as opposed to the limited trigger levels available in 16c650 and 16c750 devices. it enables the system designer to optimise the interrupt performance hence minimising the interrupt overhead. in 950 mode, a priority level 2 interrupt occurs indicating that the receiver data is available when the interrupt is not masked (ier[0]=1) and the receiver fifo level reaches the value stored in this register. 15.6 flow control levels ?fcl & fch? the fcl and fch registers are located at offsets 0x06 and 0x07 of the icr respectively enhanced software flow control using xon/xoff and hardware flow control using rts#/cts# and dtr#/dsr# are available when 950 mode trigger levels are enabled (acr[5]=1). improved flow c ontrol threshold levels are offered using flow control lower trigger level (?fcl?) and flow control higher trigger level (?fch?) registers to provide a greater degree of flexibility when optimising the flow control performance. gener ally, these facilities are only available in enhanced mode. in 650 mode, in-band flow control is enabled using the efr register. an xoff character is transmitted when the receiver fifo exceeds the upper trigger level defined by fcr[7:6] as described in section 8.1. an xon is then sent when the fifo is read down to the lower fill level. the flow control is enabled and the appropriate mode selected using efr[3:0]. in 950 mode, the flow control thresholds defined by fcr[7:6] are ignored. in this mode threshold levels are programmed using fcl and fch. when in-band flow control is enabled (defined by efr[3:0]) and the receiver fifo level (?rfl?) reaches the value programmed in the fch register, an xoff is transmitted to stop the flow of serial data . the flow is resumed when the receiver fifo fill level falls to below the value programmed in the fcl register, at which point an xon character is sent. the fcl value of 0x00 is illegal. for example if fcl and fch contain 64 and 100 respectively, xoff is transmi tted when the receiver fifo contains 100 characters, a nd xon is transmitted when sufficient characters are read from the receiver fifo such that there are 63 characters remaining. cts/rts and dsr/dtr out-of-band flow control use the same trigger levels as in-band flow control. when out-of- band flow control is enabled, rts# (or dtr#) line is de- asserted when the receiver fifo level reaches the upper limit defined in the fch and is re-asserted when the receiver fifo is drained below the lower limit defined in fcl. when 950 trigger levels are enabled (acr[5]=1), the cts# flow control functions as in 650 mode and is configured by efr[7]. however, when efr[6] is set, rts# is automatically de-asserted when rfl reaches fch and re-asserted when rfl drops below fcl. dsr# flow control is configured with acr[2]. dtr# flow control is configured with acr[4:3]. 15.7 device identification registers the identification registers is located at offsets 0x08 to 0x0b of the icr the ox16c950 offers four bytes of device identification. the device id registers may be read using offset values 0x08 to 0x0b of the indexed control register. registers id1, id2 and id3 identify the device as an ox16c950 and return 0x16, 0xc9 and 0x50 respectively. the rev register resides at offset 0x0b of icr and identifies the revision of 950 core. this register returns 0x03 for revision b of the ox16c950.
data sheet revision 1.2 page 37 ox16c950 rev b oxford semiconductor ltd. 15.8 clock select register ?cks? the cks register is located at offset 0x03 of the icr this register is cleared to 0x00 after a hardware reset to maintain compatibility with 16c550, but is unaffected by software reset. this allows the user to select a clock source and then reset the channel to work-around any timing glitches. cks[1:0]: receiver clock source selector logic [00] ? the rclk pin is selected for the receiver clock (550 compatible mode). logic [01] ? the dsr# pin is selected for the receiver clock. logic [10] ? the output of baud rate generator (internal bdout#) is selected for the receiver clock. logic [11] ? the transmitter clock is selected for the receiver. this allows ri# to be used for both transmitter and receiver. cks[2]: disable bdout# pin logic 0 ? the bdout# pin is enabled and connected to the output of the internal baud rate generator which is a nx clock used by the uart. in 16c550 compatibility mode, the baud rate generator produces a 16x clock (see tcr, section 14.3). logic 1 ? the bdout# pin is disabled and set permanently low. cks[3]: receiver 1x clock mode selector logic 0 ? the receiver is in nx clock mode as defined in the tcr register. after a hardware reset the receiver operates in 16x clock mode, i.e. 16c550 compatibility. logic 1 ? the receiver is in isochronous 1x clock mode. cks[5:4]: transmitter 1x clock or baud rate generator output (bdout) on dtr# pin logic [00] ? the function of the dtr# pin is defined by the setting of acr[4:3]. logic [01] ? the transmitter 1x clock (bit rate clock) is asserted on the dtr# pin and the setting of acr[4:3] is ignored. logic [10] ? the output of baud rate generator (nx clock) is asserted on the dtr# pin and the setting of acr[4:3] is ignored. logic [11] ? reserved. cks[6]: transmitter clock source selector logic 0 ? the transmitter clock source is the output of the baud rate generator (550 compatibility). logic 1 ? the transmitter uses an external clock applied to the ri# pin. cks[7]: transmitter 1x clock mode selector logic 0 ? the transmitter is in nx clock mode as defined in the tcr register. after a hardware reset the transmitter operates in 16x clock mode, i.e. 16c550 compatibility. logic 1 ? the transmitter is in isochronous 1x clock mode. 15.9 nine-bit mode register ?nmr? the nmr register is located at offset 0x0d of the icr the ox16c950 offers 9-bit data framing for industrial multi- drop applications. 9-bit mode is enabled by setting bit 0 of the nine-bit mode register (nmr). in 9-bit mode the data length setting in lcr[1:0] is ignored. furthermore as parity is permanently disabled, the setting of lcr[5:3] is also ignored. the receiver stores the 9th bit of the received data in lsr[2] (where parity error is stored in normal mode). note that ox16c950 provides a 128-deep fifo for lsr[3:1]. the transmitter fifo is 9-bit wide and 128 deep. the user should write the 9th (msb) data bit in spr[0] first and then write the other 8 bits to thr. as parity mode is disabled, lsr[ 7] is set whenever there is an overrun, framing error or received break condition. it is unaffected by the contents of lsr[2] (now the received 9th data bit). in 9-bit mode, in-band flow control is disabled regardless of the setting of efr[3:0] and the xon1/xon2/xoff1 and xoff2 registers are used for special character detection. interrupts in 9-bit mode: while ier[2] is set, upon receiving a character with status error, a level 1 interrupt is asserted when the character and the associated status are transferred to the fifo. the ox16c950 can assert an optional interrupt if a received character has its 9 th bit set. as multi-drop systems often use the 9 th bit as an address bit, the receiver is able to generate an interrupt upon receiving an address character. this feature is en abled by setting nmr[2]. this will result in a level 1 interrupt being asserted when the address character is transferred to the receiver fifo.
data sheet revision 1.2 page 38 ox16c950 rev b oxford semiconductor ltd. in this case, as long as there are no errors pending, i.e. lsr[1], lsr[3], and lsr[4] are clear, '0' can be read back from lsr[7] and lsr[1], thus differentiating between an ?address? interrupt and receiver error or overrun interrupt in 9-bit mode. note however that should an overrun or error interrupt actually occur, an address character may also reside in the fifo. in this case, the software driver should examine the contents of the receiver fifo as well as process the error. the above facility produces an interrupt for recognizing any ?address? characters. alternativ ely, the user can configure ox16c950 to match the receiver data stream with up to four programmable 9-bit characters and assert a level 5 interrupt after detecting a match. the interrupt occurs when the character is transferred to the fifo (see below). nmr[0]: 9-bit mode enable logic 0 ? 9-bit mode is disabled. logic 1 ? 9-bit mode is enabled. nmr[1]: enable interrupt when 9 th bit is set logic 0 ? receiver interrupt for detection of an ?address? character (i.e. 9 th bit set) is disabled. logic 1 ? receiver interrupt for detection of an ?address? character (i.e. 9 th bit set) is enabled and a level 1 interrupt is asserted. special character detection while the uart is in both 9-bit mode and enhanced mode, setting ier[5] will enable detection of up to four ?address? characters. the least significant eight bits of these four programmable characters are st ored in special characters 1 to 4 (xon1, xon2, xoff1 and xoff2 in 650 mode) registers and the 9 th bit of these characters are programmed in nmr[5] to nmr[2] respectively. nmr[2]: bit 9 of special character 1 nmr[3]: bit 9 of special character 2 nmr[4]: bit 9 of special character 3 nmr[5]: bit 9 of special character 4 nmr[7:6]: reserved bits 6 and 7 of nmr are always cleared and reserved for future use. 15.10 modem disable mask ?mdm? the mdm register is located at offset 0x0e of the icr this register is cleared after a hardware reset to maintain compatibility with 16c550. it allows the user to mask interrupts and control sleep operation due to individual modem lines or the serial input line. mdm[0]: disable delta cts logic 0 ? delta cts is enabled. it can generate a level 4 interrupt when enabled by ier[3]. delta cts can wake up the uart when it is asleep under auto-sleep operation. logic 1 ? delta cts is disabled. it can not generate an interrupt or wake up the uart. mdm[1]: disable delta dsr logic 0 ? delta dsr is enabled. it can generate a level 4 interrupt when enabled by ier[3]. delta dsr can wake up the uart when it is asleep under auto-sleep operation. logic 1 ? delta dsr is disabled. in can not generate an interrupt or wake up the uart. mdm[2]: disable trailing edge ri logic 0 ? trailing edge ri is enabled. it can generate a level 4 interrupt when enabled by ier[3]. trailing edge ri can wake up the uart when it is asleep under auto-sleep operation. logic 1 ? trailing edge ri is disabled. in can not generate an interrupt or wake up the uart. mdm[3]: disable delta dcd logic 0 ? delta dcd is enabled. it can generate a level 4 interrupt when enabled by ier[3]. delta dcd can wake up the uart when it is asleep under auto-sleep operation. logic 1 ? delta dcd is disabled. in can not generate an interrupt or wake up the uart. mdm[7:4]: reserved these bits must be set to ?0000? 15.11 readable fcr ?rfc? the rfc register is located at offset 0x0f of the icr this read-only register returns the current state of the fcr register (note that fcr is write-only). this register is included for diagnostic purposes.
data sheet revision 1.2 page 39 ox16c950 rev b oxford semiconductor ltd. 15.12 good-data status register ?gds? the gds register is located at offset 0x10 of the icr good data status is set when the following conditions are true: ? isr reads level0 (no interrupt), level2 or 2a (receiver data) or level3 (thr empty) interrupt. ? lsr[7] is clear i.e. no parity error, framing error or break in the fifo. ? lsr[1] is clear i.e. no overrun error has occurred. gds[0]: good data status gds[7:1]: reserved 15.13 dma status register ?dms? the dms register is located at offset 0x11 of the icr. this allows the txrdy# and rxrdy# lines to be permanently deasserted, and the current internal status to be monitored. this mainly has applications for testing. dms[0]: rxrdy status read only: set when rxrdy is asserted (pin driven low). dms[1]: txrdy status read only: set when txrdy is asserted (pin driven low). dms[5:2] reserved dms[6]: force rxrdy inactive logic 0 ? rxrdy# acts normally logic 1 ? rxrdy# is permanently inactive (high) regardless of fifo thresholds dma[7]: force txrdy inactive logic 0 ? txrdy# acts normally logic 1 ? txrdy# is permanently inactive (high) regardless of fifo thresholds. 15.14 port index register ?pix? the pix register is located at offset 0x12 of the icr. this read-only register gives the uart index. for a single channel device such as the ox16c950 this reads ?0?. 15.15 clock alteration register ?cka? the cka register is located at offset 0x13 of the icr. this register adds additional clock control mainly for isochronous and embedded applicat ions. the register is effectively an enhancement to the cks register. this register is cleared to 0x00 after a hardware reset to maintain compatibility with 16c550, but is unaffected by software reset. this allows the user to select a clock mode and then reset the channel to work-around any timing glitches.
data sheet revision 1.2 page 40 ox16c950 rev b oxford semiconductor ltd. 16 o perating c onditions symbol parameter min. max. units v dd dc supply voltage -0.3 7.0 v v in dc input voltage -0.3 v dd + 0.3 v i in dc input current +/- 10 ma t stg storage temperature -40 125 c table 20: absolute maximum ratings symbol parameter min max units v dd dc supply voltage 3 5.25 v t o operating temperature range 0 70 c table 21: recommended operating conditions n.b. under 3v operation some inputs are 5v tolerant (i/o signals, cpu interface, and uart signals). 17 dc e lectrical c haracteristics 17.1 5v operation . symbol parameter condition min. max. units v dd supply voltage commercial 4.75 5.25 v v ih input high voltage ttl interface note1 ttl schmitt trigger 2.0 2.4 v v il input low voltage ttl interface note 1 ttl schmitt trigger 0.8 0.6 v c il capacitance of input buffers 5.0 pf c ol capacitance of output buffers 10.0 pf i ih input high leakage current v in = v dd -10 10 a i il input low leakage current v in = v ss -10 10 a v oh output high voltage i oh = 1 a v dd ? 0.05 v v oh output high voltage i oh = 4 ma note2 2.4 v v ol output low voltage i ol = 1 a 0.05 v v ol output low voltage i ol = 4 ma note2 0.4 v i oz 3-state output leakage current -10 10 a i st static current v in = v dd or v ss 45 100 a i cc operating supply current in normal mode note3 f ck = 1.8432 mhz f ck = 7.372 mhz f ck = 60.00 mhz 0.40 1.50 10.0 2.0 5.0 30.0 ma operating supply current in sleep mode note3 f ck = 1.8432 mhz f ck = 7.372 mhz f ck = 60.00 mhz 0.35 1.25 3.5 0.5 2.0 5.0 table 22: dc electrical characteristics note 1: all input buffers are ttl with the except ion of reset which is a schmitt trigger buffer. note 2: i oh and i ol are 12 ma for db[7:0] and 4 ma for all other outputs. note 3: for further details on operating current please refer to the?ox16c95x test document?.
data sheet revision 1.2 page 41 ox16c950 rev b oxford semiconductor ltd. 17.2 3v operation these figures assume the tqfp package, with vsel applied for 3v operation. i/o signals, cpu interface and uart signals are 5v tolerant. symbol parameter condition min. max. units v dd supply voltage commercial 3.0 3.45 v v ih input high voltage ttl interface note1 ttl schmitt trigger 0.7 v dd tbd v dd + 0.5 tbd v v il input low voltage ttl interface note 1 ttl schmitt trigger -0.5 tbd 0.2 v dd tbd v c il capacitance of input buffers 5.0 pf c ol capacitance of output buffers 10.0 pf i ih input high leakage current v in = v dd -1 1 a i il input low leakage current v in = v ss -1 1 a v oh output high voltage i oh = 1 a v dd ? 0.05 v v oh output high voltage i oh = 4 ma note2 2.4 v v ol output low voltage i ol = 1 a 0.05 v v ol output low voltage i ol = 4 ma note2 0.4 v i oz 3-state output leakage current -1 1 a i st static current v in = v dd or v ss 45 100 a i cc operating supply current in normal mode note3 f ck = 1.8432 mhz f ck = 7.372 mhz f ck = 60.00 mhz tbd tbd ma operating supply current in sleep mode note3 f ck = 1.8432 mhz f ck = 7.372 mhz f ck = 60.00 mhz tbd tbd table 23: dc electrical characteristics note 1: all input buffers are ttl with the except ion of reset which is a schmitt trigger buffer. note 2: i oh and i ol are 6 ma for db[7:0] and 2 ma for all other outputs. note 3: for further details on operating current please refer to the?ox16c95x test document?.
data sheet revision 1.2 page 42 ox16c950 rev b oxford semiconductor ltd. 18 ac e lectrical c haracteristics 18.1 5v operation symbol parameter min max units t sa address set-up time to ior# or iow# falling address set-up time to ior or iow rising 0 ns t ha address hold time after ior# or iow# rising note1 address hold time after ior or iow falling note1 0 ns t sc chip select set-up time to ior# or iow# falling chip select set-up time to ior or iow rising 0 ns t hc chip select hold time after ior# or iow# rising note1 chip select hold time after ior or iow falling note1 0 ns t r1 pulse duration of ior# or ior 25 ns t r2 delay between ior# rising and ior#/iow# falling delay between ior falling and ior/iow rising 38 t acc access time; data valid after ior# falling or ior rising 20 ns t df data bus floating after ior# rising or ior rising 10 ns t w1 pulse duration of iow# or iow 25 ns t w2 delay between iow# rising and ior# /iow# falling delay between iow falling and ior/iow rising 38 ns t sd data set-up time to iow# rising or iow falling 0 ns t hd data hold time after iow# rising or iow falling 3 ns t sac address and chip select set-up time to ads# rising note2 0 ns t hac address and chip select hold time after ads# rising note2 2 ns t a1 pulse duration of ads# note2 2 ns t had ior#/iow# rising or ior/iow falling to ads# falling note3 ns t irs sin set-up time to isochronous input clock ?rx_clk_in rising note4 1 ns t irh sin hold time after isochronous input clock ?rx_clk_in? rising note4 3 ns t its sout valid after isochronous output clock ?tx_clk_out? falling note4 0 4 ns table 24: ac electrical characteristics note 1: t ha and t hc timing constrains only apply to non-multiplexed arrangement where ads# is permanently tied low. note 2: ads# signal may be tied low if addres s is stable during re ad or write cycles. note 3: t had, t a1 and t sac timing constrains only apply to multiplexed arrangement where ads# is used. note 4: in isochronous mode, transmitter data is available af ter the falling edge of the x1 clock and the receiver data is samp led using the rising edge of the x1 clock. the system designer is should ensure that mark-to-space ratio of the x1 clock is such that the req uired set-up and hold timing constraint are met. one way of achieving this is to choose a crystal frequency which is twice the requir ed data rate and then divide the clock by two using the on-board prescaler . in this case the mark-to-sp ace ratio is 50/50 for the purpo se of set-up and hold calculations.
data sheet revision 1.2 page 43 ox16c950 rev b oxford semiconductor ltd. 18.2 3v operation n.b. maximum frequency of operation is downgraded under 3v operation to 50 mhz. symbol parameter min max units t sa address set-up time to ior# or iow# falling address set-up time to ior or iow rising 0 ns t ha address hold time after ior# or iow# rising note1 address hold time after ior or iow falling note1 0 ns t sc chip select set-up time to ior# or iow# falling chip select set-up time to ior or iow rising 0 ns t hc chip select hold time after ior# or iow# rising note1 chip select hold time after ior or iow falling note1 0 ns t r1 pulse duration of ior# or ior 35 ns t r2 delay between ior# rising and ior#/iow# falling delay between ior falling and ior/iow rising 45 t acc access time; data valid after ior# falling or ior rising 28 ns t df data bus floating after ior# rising or ior rising 12 ns t w1 pulse duration of iow# or iow 35 ns t w2 delay between iow# rising and ior# /iow# falling delay between iow falling and ior/iow rising 45 ns t sd data set-up time to iow# rising or iow falling 0 ns t hd data hold time after iow# rising or iow falling 4 ns t sac address and chip select set-up time to ads# rising note2 0 ns t hac address and chip select hold time after ads# rising note2 2 ns t a1 pulse duration of ads# note2 3 ns t had ior#/iow# rising or ior/iow falling to ads# falling note3 45 ns t irs sin set-up time to isochronous input clock ?rx_clk_in rising note4 2 ns t irh sin hold time after isochronous input clock ?rx_clk_in? rising note4 4 ns t its sout valid after isochronous output clock ?tx_clk_out? falling note4 0 6 ns table 25: ac electrical characteristics note 1: t ha and t hc timing constrains only apply to non-multiplexed arrangement where ads# is permanently tied low. note 2: ads# signal may be tied low if addr ess is stable during re ad or write cycles. note 3: t had, t a1 and t sac timing constrains only apply to multiplexed arrangement where ads# is used. note 4: in isochronous mode, transmitter data is available a fter the falling edge of the x1 clock and the receiver data is samp led using the rising edge of the x1 clock. the system designer is should ensure that mark-to-space ratio of the x1 clock is such that the req uired set-up and hold timing constraint are met. one way of achieving this is to choose a cr ystal frequency which is twice the requir ed data rate and then divide the clock by two using the on-board prescaler . in this case the mark-to-sp ace ratio is 50/50 for the purpo se of set-up and hold calculations.
data sheet revision 1.2 page 44 ox16c950 rev b oxford semiconductor ltd. 19 t iming w aveforms ads# t sa t sc t r1 t ha t hc t acc t r2 t df a[2:0] cs0 cs1 cs2# ior# ior db[7:0] data valid address valid t dh t sac t a1 t hac t had asserted de-asserted de-asserted figure 4: read cycle timing ads# t sa t sc t w 1 t ha t hc t sd t w 2 t hd a[2:0] cs0 cs1 cs2# iow# iow db[7:0] data valid address valid t sac t a1 t hac t had asserted de-asserted de-asserted figure 5: write cycle timing
data sheet revision 1.2 page 45 ox16c950 rev b oxford semiconductor ltd. t irs t irh sin rx_clk_in (dsr#) t its sout tx_clk_out (dtr#) figure 6: isochronous mode timing
data sheet revision 1.2 page 46 ox16c950 rev b oxford semiconductor ltd. 20 p ackage i nformation figure 7: 44 pin plastic leaded chip carrier OX16C950-PCC60-B
data sheet revision 1.2 page 47 ox16c950 rev b oxford semiconductor ltd. figure 8: 48 pin thin quad flat pack (48 tqfp) 21 o rdering i nformation OX16C950-PCC60-B revision operating conditions -commercial package type - 44 p l c c ox16c950-tqc60-b revision package material - p lastic package type - 48 tq fp ox16c950-tqc60-b
data sheet revision 1.2 page 48 ox16c950 rev b oxford semiconductor ltd. n otes this page has intentionally been left blank.
?copyright oxford semico nductor ltd 1998-2001 oxford semiconductor ltd believes the information contained in this document to be accurate and reliable. however, it is subjec t to change without notice. no responsibility is assumed by oxford semiconductor for its use, nor for infringement of patents or other rights of third parties. no part of this publication may be reproduced, or transmitted in any form or by any means withou t the prior consent of oxford semiconductor ltd. oxford semico nductor?s terms and conditions of sale apply at all times. c ontact d etails oxford semiconductor ltd. 25 milton park abingdon oxfordshire ox14 4sh united kingdom telephone: +44 (0)1235 824900 fax: +44 (0)1235 821141 sales e-mail: sales@oxsemi.com web site: http://www.oxsemi.com

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